Agile Analog launches analogue IP subsystem

Agile Analog, the customisable analogue IP company, is launching the first complete analogue IP subsystem for RISC-V applications.

This process agnostic, customisable and digitally wrapped analogue IP subsystem will help solve many of the issues that SoC designers currently encounter, as it pairs with a RISC-V core to form a complete solution.

“The RISC-V architecture is enabling a surge of new SoC product developments, and the demand for more accessible and configurable IP solutions is increasing. One of the major challenges that digital chip designers face is in integrating the analog circuitry to support their SoC designs,” says Agile’s Chris Morrison, “with our RISC-V analog IP subsystem, it’s possible to access the appropriate analog IP for a specific process and foundry. This can then be integrated seamlessly with digital IP from a digital IP provider in the RISC-V space, simplifying chip design and accelerating the time to market for new RISC-V IoT applications. As with all of the Agile Analog IP, this subsystem is customisable to give the exact feature set required for the application.”

This analogue IP subsystem is verified in both analogue and digital environments, connects directly to the MCU’s peripheral bus, and is supplied with a SystemVerilog model for easy integration into an SoC’s existing digital verification environment.

Agile Analog’s initial RISC-V subsystem macro for IoT applications is available now consisting of the following sub-blocks:

agilePMU

The agilePMU Subsystem is an efficient and highly integrated power management unit for SoCs/ASICs. Featuring a power-on-reset, multiple low drop-out regulators, and an associated reference generator, this is designed to ensure low power consumption while providing optimal power management capabilities. Equipped with an integrated digital controller, this subsystem offers precise control over start-up and shutdown, supports supply sequencing, and allows for individual programmable output voltage for each LDO. Status monitors provide real-time feedback on the current state of the subsystem, ensuring optimal system performance.

agileSMU

The agileSMU Subsystem is a low power integrated macro consisting of the essential IP blocks required to securely manage waking up a SoC from sleep mode. Typically containing a programmable oscillator for low frequency SoC operation and RTC, a number of low power comparators which can be used to initiate the wake-up sequence, and a power-on-reset which provides a robust, start-up reset to the SoC. Equipped with an integrated digital controller, this subsystem offers precise control over wake-up commands and sequencing. Status monitors provide real-time feedback on the current state of the subsystem, ensuring optimal system performance over the full product lifecycle.

agileSensorIF

The agileSensorIF Subsystem is a low power integrated macro providing all the analog required to interface with external sensors. Featuring two up-to 12-bit and 64 MSPS SAR ADCs, a 12-bit DAC and multiple programmable comparators, this sensor interface provides all the connections needed to interface with the outside world. Integrated programmable gain amplifiers and buffers support a wide range of external sensors and systems. It is equipped with an integrated digital controller and status monitors to provide real-time feedback on the current state of the subsystem, ensuring optimal system performance over the full product lifecycle

View more : IGBT modules | LCD displays | electronic components