Benefits of the Lattice Nexus FPGA Technology Platform in Mission-Critical Applications

“The industrial, automotive, communications, aerospace and security markets are increasingly demanding mission-critical applications. Today, the Lattice NexusTM technology platform provides absolute advantages for FPGAs used in Mission-critical applications.

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The industrial, automotive, communications, aerospace and security markets are increasingly demanding mission-critical applications. Today, Lattice Nexus^TMThe technology platform provides absolute advantages for FPGAs used in mission-critical applications.

Introduction (MPU vs. FPGA)

Today’s mission-critical systems can require considerable computing power. One computing solution is the use of microprocessor units (MPUs), such as PCs and workstations. Although such processors may seem powerful, in reality they only perform simple tasks, such as adding two numbers or comparing the magnitude of two numbers. Again, they appear to be fast because the system clock is running at 2.4 GHz or higher.

The crux of the matter is that, while MPUs can handle decision-making tasks well, they are not as efficient at performing many data-processing tasks. As a result, MPUs tend to consume more power and generate more heat when performing such tasks.

A more efficient way to implement signal and data processing in embedded applications is to use Field Programmable Gate Arrays (FPGAs). FPGAs benefit from their own parallel architecture and can perform data processing operations in parallel with low latency. As the column “FPGA Basics: What is an FPGA?” Why do you need an FPGA? ” states: “The heart of any FPGA lies in its programmable fabric, which takes the form of an array of programmable logic modules. Each logic module contains multiple elements: a look-up table (LUT), a multiplexer, and a registers, all of which can be configured (programmed) to perform the function the user desires.”

Figure 1. General-purpose FPGA programmable architecture (Image credit: Max Maxfield)

A more vivid way of describing it is to think of programmable logic as “islands” in an “ocean” of programmable interconnects. Groups of programmable logic blocks can be configured to perform desired logic functions, while programmable interconnects connect the logic blocks to each other and to the main general-purpose input/output interface (GPIO).

It should be noted that the above description is an extremely simplified case. In addition to programmable architectures, FPGAs can contain memory blocks equivalent to terabytes of RAM, as well as numerous digital signal processing (DSP) units. Likewise, in addition to general-purpose I/O, FPGAs can include high-speed SERDES modules that support gigabit serial interfaces and high-speed interfaces to external memory.

One of the main reasons why FPGAs are widely known is that their programmable logic can be configured to execute the corresponding data processing algorithms in a massively parallel fashion, which is not only orders of magnitude faster than MPUs, but also consumes very little power. Also, unlike SoCs where algorithms are “frozen in the chip”, FPGA designs can be reconfigured at any time. Furthermore, since user IP is programmed by the end user, FPGAs are manufactured without any user IP, which enables FPGAs to be shipped in an unprotected supply chain without user IP being stolen or tampered with. This is also different from SOC and ASIC. Therefore, FPGAs are ideal for mission-critical systems including industrial robotics and communication infrastructure equipment.

Radiation Challenge

In order to expand capacity, improve performance, reduce power consumption and cost, transistors are getting smaller and smaller with each new generation of chips. Structures fabricated in chips today are only tens of nanometers (nm) in size (a nanometer is one billionth of a meter). These structures are so tiny that they can be affected by radiation on Earth.

In addition, systems for mission-critical applications are typically deployed in environments with persistently high levels of radiation, including high latitudes and even space.

For such applications, two radiation effects are most critical: the single event effect (SEE) and the total ionizing dose effect (TID).

SEE refers to the immediate effect caused in an integrated circuit by a single ionized particle (electron, proton, ion, photon, etc.). Handling SEE requires rapid recovery when radiation occurs. In contrast, TID eventually causes the semiconductor lattice to age due to the accumulation of long-term exposure to radiation. Typical TID effects include transistor switching threshold shift, increased leakage current, performance degradation, and ultimately functional failure. Therefore, solving TID requires long-term resistance to radiation and recovery from it.

Single-event upset (SEU) is a case of SEE in which high-energy particles strike sensitive nodes in a microcircuit and cause a state change. For example, a SEU may cause a register cell or memory cell to toggle from a logic 0 to a logic 1 or from a logic 0 to a 0. Unlike the problems caused by TID, SEU is defined as a “soft error” because it can be corrected.

Figure 2. Single event upset (SEU) in sequential logic (Image credit: Max Maxfield)

Unfortunately, more and more advanced manufacturing process will lead to a more serious trend of multi-unit inversion (MCU). This means that SEUs may actually flip multiple storage elements logically due to the very tight arrangement of structures in the chip. In addition, multiple-bit flipping (MBU) refers to an MCU that occurs within the same data word or frame, which can negatively impact the error correction capability of the system.

Another form of SEE is a single event transient (SET), which is a pulse (also known as a glitch or spike) formed by radiating particles affecting a portion of combinatorial logic.

Figure 3. Single Event Transient (SET) in Combinatorial Logic (Image credit: Max Maxfield)

SET itself isn’t much of a problem, as it’s usually gone before the rest of the system detects it. Having said that, if a SET happens to happen at the wrong time, it may be clocked into a register element or memory cell, at which point it becomes a SEU.

Another potential problem is single event lock-in (SEL). SEE can cause a low impedance path (actually a short) between the power and ground rails of a CMOS circuit. If this happens, the device needs to be restarted immediately (power off and on) to prevent serious damage to it. It goes without saying that power cycling a mission critical device can cause a lot of problems in many cases.

Further consideration is required for FPGAs. In addition to register elements and RAM cells, FPGAs also include configuration cells, programmable interconnects, and programmable general-purpose I/Os for configuring programmable logic blocks. And the configuration unit technology used by different FPGAs is not the same.

Lattice offers a new SRAM-based device developed using the Lattice Nexus FPGA technology platform, which provides an absolute advantage for implementing advanced systems for mission-critical applications.

Nexus Technology Platform

Lattice’s Nexus technology platform, based on the 28nm FD-SOI process, provides a significant differentiator for the FPGA market.

The FD-SOI process directly brings two important advantages. First, due to the use of a fully depleted process, the chip itself has strong radiation resistance. FD-SOI is inherently immune to single-event lock-in, which means no downtime in mission-critical applications, which typically requires a power cycle to lift.

The second notable advantage is flexibility. By changing the bias voltage of the substrate, the user can choose to operate in high performance (HP) or low power (LP) mode. In addition, the system can be switched between the two modes in real time through program control.

For example, we have discussed before that when radiation passes through a register element or memory cell in the form of high-energy particles, a single-event flip occurs, ionizing (creating an electric charge) the semiconductor material, creating a brief pulse of electrical current. Such pulses may be enough to disturb the stored data.

Observe the bulk CMOS process as shown in Figure 4(a). Radiation (red arrows) creates an ionizing path through the chip, leaving positive and negative charges behind. These charges then accumulate at the point of incidence (blue arrows).

Figure 4. Comparison of the impact of SEU on Bulk CMOS process (a) and FD-SOI process (b)

In contrast, let’s look at the FD-SOI process shown in Figure 4(b). In this case, the oxide layer (yellow) isolates the generated charge since any charge under the oxide layer (yellow) cannot collect at the sensitive node. Less charge means that transient current pulses are also weaker and less likely to fail register elements or memory cells.

Another potential problem mentioned earlier is the MCU and MBU, where a single particle can destroy multiple storage elements. In the Bulk CMOS process shown in Figure 5(a), radiation (red arrows) creates an ionization path through the chip, leaving positive and negative charges behind. In addition to accumulating at the incident node (blue arrows), these charges may also accumulate at adjacent nodes (purple arrows), leading to MCU or MBU.

Figure 5. Bulk CMOS process (a) is susceptible to MCU and MBU, while FD-SOI process (b) prevents these disturbances

In contrast, let’s examine the FD-SOI process shown in Figure 5(b). In addition to isolating the incident node from most of the generated charge, the buried oxide layer (yellow) greatly shrinks the sensitive area of ​​each cell, making it difficult for a single particle trajectory to affect multiple data bits, greatly reducing the The occurrence of MCU and MBU.

Designers of mission critical and safety systems often use the concept of FIT (failure rate). The FIT of a device is defined as the device in billion (10⁹) number of failures that can be expected in an hour of operation (e.g., one device runs for a billion hours, 1000 devices run for 1 million hours each, a million devices run for 1000 hours each, and so on).

For FPGAs using Bulk CMOS technology at the 28nm technology node, the FIT is about 100. In contrast, the same 28nm process, the Lattice FPGA using the Nexus platform FD-SOI process has a FIT of only 1. This means that the Nexus platform reduces FIT by two orders of magnitude. FPGAs based on Nexus platforms such as Lattice CrossLink™-NX provide detailed SEU characterization reports that can be used to estimate failure rates due to radiation effects.

With its own advantages, the Nexus platform makes FPGAs based on this technology truly stand out and better serve the medical, automotive, security and other fields. However, this is just the beginning, as Lattice’s mission is to reduce FIT to almost zero, which can be achieved by enhancing the FD-SOI process and the technologies discussed below.

Lattice Nexus FPGA

Error Correcting Code (ECC) memory is a way of storing data that can detect and correct any internal data corruption, such as that caused by radiation. Since SEU is called “soft error”, there are concepts of soft error detection (SED) and soft error correction (SEC).

Meanwhile, memory scrubbing refers to reading data from each storage location, correcting bit errors (if any) using error-correcting codes, and then writing the corrected data back to the same location. Memory scrubbing is commonly used in mission-critical and security systems and systems susceptible to high radiation environments.

Designers often have to implement the memory scrubbing function themselves, which consumes valuable programmable logic resources. In contrast, Nexus FPGAs already include dedicated IP blocks that automate ECC-based memory scrubbing in the background.

In addition, Nexus FPGAs have a built-in SED/SEC module in configuration memory, enabling fast frame-by-frame detection and error correction without the need for external circuitry. Although such errors are rare, they are still theoretically possible. If radiation somehow causes the hive state to flip, this dedicated IP will flip it back.

Therefore uncorrectable SEUs have not been observed in Lattice Nexus FPGAs. The underlying process reduces the theoretical FIT to 1, which means that it is still possible to experience a bit error situation, but the affected bit will return to normal almost immediately.

Nonetheless, it is possible that the internal SED/SEC engine may not be able to correct errors. The first is the occurrence of multiple individual SEUs, where two or more particles randomly scramble multiple digits within the same data frame. The second situation is the occurrence of MBU, where a single particle makes two or more digits in the same data frame abnormal.

When analyzing the Nexus platform against the effects of MCU and MBU radiation, pay special attention to these effects. These tests confirmed the technical advantages described above, showing that a single particle rarely affects multiple cells. Additionally, due to Lattice’s memory array design, all observed MCUs appear in different data frames, allowing corrections by the SED/SEC engine.

In addition to testing Nexus FPGAs with real radiation sources, these devices provide mechanisms that allow system developers to inject simulated radiation themselves. In fact, developers can enter single-bit and multi-bit errors synchronously or asynchronously. Through these mechanisms, developers can verify the operation of memory scrubbing and SED/SEC engines, as well as device operation and generating correct data, ensuring that devices and designs perform as expected even in harsh, radiation-dense environments.

in conclusion

Like all Electronic components, FPGAs can be negatively affected by radiation, which becomes more pronounced as structures in chips continue to shrink. Based on the 28nm FD-SOI process, the Lattice Nexus technology platform allows users to select high-performance or low-power modes of operation and make changes in real-time through program control. In addition, because the FD-SOI process is inherently radiation-hardened, its failure rate FIT is only 1, which is two orders of magnitude higher than standard CMOS FPGAs under the same technology node.

For these reasons, Lattice Nexus FPGAs are ideal for mission-critical and safety applications in commercial, industrial, communications, security and automotive.