CPO market to grow at 46% 2022-33

To accelerate data movement in AI/ML gear is the main driver for adopting optical interconnects for next-generation HPC systems.

“Pluggable form factors will be limited in their ability to support 6.4T and 12.8T capacity in terms of required electrical and optical densities, thermal management, and energy efficiency,” says Yole’s Martin Vallo, “as a result of discrete electrical device implementation, power dissipation, and thermal management are becoming limiting factors for future pluggable optics. Co-packaging using a silicon photonics technology platform aims to overcome the challenges”.

Optics are coming closer and closer to the chipset. Bringing in data using light to the point where it is centrally processed is one of the main goals of architecture designers.

This trend started a decade ago with proprietary designs for optical assemblies mounted on PCBs.

The idea of these EOIs (Embedded Optical Interconnects) has continued in the COBO (Consortium for On-Board Optics), which has developed specifications to permit the use of board-mounted optical modules in the manufacturing of networking equipment.

CPO is an innovative approach that brings the optics and the switch ASIC very close together. Since it is challenging with today’s technology to surround the 50T switch chip with 16 3.2Tbps optical modules.

NPO (Near Packaged Optics) tackles this by using a high-performance PCB substrate – an interposer – that sits on the host board, in contrast to CPO, where the modules surround the chip on a multi-chip module substrate.

The NPO interposer is more spacious, making the signal routing between the chip and optical modules easier while still meeting signal integrity requirements.

In contrast, CPO confines the modules and host ASIC much closer to each other with lower channel loss and power consumption.

“Networking hardware is seeing more common components as technology advances enable tighter integration of communication and computing technologies in commercial systems,” says Yole’s Eric Mounier, “ moreover, AI models are growing in size at an unprecedented rate, and the capabilities of the traditional architectures – copper-based electrical interconnects – for chip-to-chip or board-to-board will become the main bottleneck for scaling machine learning”.

As a result, new very-short-reach optical interconnects have emerged for HPC and its new disaggregated architecture. Disaggregated design distinguishes the compute, memory, and storage components found on a server card and pools them separately.

Using advanced in-package optical I/O technology to interconnect xPUs , specifically CPUs , DPUs , GPUs , FPGAs , and ASICs, with memory and storage can help to achieve the necessary transmission speeds and bandwidths.

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