Cryo-IP for quantum computing

SureCore is using these to develop IP to enable the design of cryo-control ASICs for use in quantum computing.

The challenge is the effective control of qubits which will operate at cryogenic temperatures, typically around 4K, in the confines of a cryostat.

The control electronics needed to manipulate the qubits is often located outside the cryostat and can currently only function near to room temperature.

This is because silicon ICs are only specified to operate from -40°C to 125°C (233K to 398K).

Connecting the two requires expensive and bulky cabling, and the amount of cabling required for all the qubits presents a fundamental barrier to quantum computing scaling aside from the inherent latency impact.

To achieve the necessary increase in  the number of qubits, the control electronics must be co-located with the qubits in the cryostat.

However, given the restricted temperature range of current silicon ICs, this is currently not an option.

The aim of this project is to understand and model changes in transistor behaviour at cryo temperatures, produce a suite of recharacterized transistor models and then use these to design a portfolio of CryoCMOS IP to facilitate the development of custom chips that can directly interface to the qubits inside the cryostat at cryogenic temperatures.

One of the key transistor parameters affected by plunging temperatures is the threshold voltage (Vt).

As the temperature is lowered, the Vt increases substantially, pushing transistor selection towards low and super-low Vt variants (LVt/SLVt).

In order to further ease this design challenge, the GLOBALFOUNDRIES 22nm FDSOI (22FDX) process node was selected for this project. FDSOI is an ideal technology choice that allows optimal cryogenic design by enabling adjustments to the threshold voltage to be made by altering the back bias.

SeniWise, a partner in the CryoCMOS Consortium, has developed new transistor models including both Typical-Typical (TT) transistors as well as corners (Slow-Slow, SS & Fast-Fast, FF) that will enable reliable circuit design for use at 4K and 77K.

“Standard CMOS is characterised over the usual performance parameters of -40°C to +125°C. So, taking standard CMOS down to 4K or -270°C is a major step into new territory where the operating characteristics of the transistors change markedly’” says SemiWise CEO Prof Asen Asenov.

SemiWise will re-centre the foundry transistor SPICE models for cryogenic temperatures so that the 22FDX node can be used for cryogenic circuit design.

SemiWise’s re-centring technology allows the development of typical and corner transistor models as well as statistical mismatch models, all critical to the SRAM design process.

Based on these re-centred cryogenic transistor models, sureCore is exploiting its low power design expertise to develop a suite of power-optimised  IP including Standard Cells, SRAM, ROM and Register Files.

Low power is a critical design criterion as power consumption translates to unwelcome heating effects which places additional cooling burdens on the cryostat.

Innovate UK awarded a grant of £6.5 million to the CryoCMOS Consortium.

This project will help to make cryo-IP available to all UK companies involved in quantum computing.

By forming a team of UK leaders in the field, the project expects to be able to achieve results in less than three years rather than the many years it would take working as individuals.

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