DDR5 Memory Innovation: Unveiling the Sub-Channel Concept for Enhanced Efficiency

Why was the concept of sub-channels designed for DDR5, and what was the original intention behind the design of sub-channels? With a sub-channel’s bandwidth being 32 bits, does it mean that two channels need to work simultaneously to form a 64-bit cache line?

First, let’s introduce two concepts:

1. Burst Length: Burst refers to the method of consecutive data transfer in adjacent storage units within the same row. The number of consecutive transfer cycles is called Burst Length (BL).

   For DDR3 and DDR4 memory, BL is 8; for DDR5 memory, BL is 16.

2. Cache line: We know that the CPU cannot directly read data from memory. To read data from memory, the CPU first needs to load the data from memory into the high-speed cache, and then read the data from the cache.

   We divide a cache into many equal-sized blocks, and each block’s size is called a cache line.

   For example, for a 32-byte cache, if we divide it into 32 blocks, each cache line is 1 byte, with a total of 32 cache lines. If we divide it into 8 blocks, the cache line size is 4 bytes, with a total of 8 cache lines.

   The cache line is the smallest unit of data transfer between the cache and memory. What is the smallest unit?

   For example, the minimum unit for caching data from memory is 64 bytes. When the cache needs to read a 32-byte data from memory, it won’t just read the 32 bytes; instead, it reads 64 bytes together.

   For X86 architecture CPUs, the cache line size is exactly 64 bytes.

In the case of DDR4, the data bus width is 64 bits, meaning we read and write 64 bits of data at a time. The highest Burst Length for each read/write is 8 bits, which results in 64 bits * 8 = 512 bits = 64 bytes, matching the cache line size of X86 architecture CPUs.

Now, with DDR5, the highest Burst Length for each read/write has increased to 16 bits. If we still maintain a 64-bit channel width, the calculation would be 64 bits * 16 = 1024 bits, which exceeds the traditional size of the CPU cache line. If we were to continue with this approach, significant changes would be required in the memory controller architecture, from the underlying hardware to the software handling data read/write operations. To address this, DDR5 introduces the concept of sub-channels.

Each sub-channel has an effective data width of 32 bits, and 32 bits * 16 (Burst Length) = 512 bits. This meets the requirement of the CPU cache line. Therefore, the introduction of sub-channels in DDR5 is intended to address this issue.