Design of Digital Circuit of Acoustic Detection System Based on CPLD Chip and DSP Chip

“The digital circuit design of the acoustic detection system based on TMS320VC33-150 makes full use of the powerful floating-point computing capability of TMS320VC33-150, and completes the algorithm processing of sound source target detection and positioning. At the same time, the logic control function of CPLD and the abundant peripheral resources of MCU are fully utilized, and the DSP algorithm and interrupt service routine flow are designed. The system has been debugged and fully field tested. The results show that the system works stably and all the indicators basically meet the requirements.

“

Authors: Zhang De, Hou Zhiguo, Jiang Li, Zhang Xianghui, Luo Xiaosong

Passive sound source detection and localization technology is a technology that uses an acoustic microphone array and an Electronic device to receive the radiated noise of a moving target to determine the location of the target.

This paper is based on the principle of sound detection technology and mature microelectronic technology, using TI’s 32-bit floating-point DSP chip TMS320VC33-150 to achieve the sound source target detection and positioning algorithm, and supplemented by ADC, CPLD, microcontroller and other devices to achieve Realize the acquisition of sound source signal, system logic control and communication functions. As to the logic control function of digital circuit, this text chooses CPLD chip EPM7128AETC100-10 of Altera Company to realize. The chip has low power consumption, abundant resources, and fixed internal delay, which is helpful for the design of sequential logic circuits. The system is mainly divided into two parts: the hardware realization of the digital circuit of the acoustic detection system and the DSP software design. The system has been debugged, runs stably, and has a good detection effect.

System functions

The sound detection system obtains the radiation noise information of the sound source target through the microphone array. After processing the front-end analog signal, the DSP performs high-speed sound detection and positioning algorithm processing in the digital circuit, and sends the obtained sound source position, speed and other information to send Cross-Display to the computer terminal.

Hardware Design of Sound Detection System

In the sound detection system, the digital circuit is the most critical part. This paper completes the hardware design of the digital circuit of the acoustic detection system with DSP, CPLD and single-chip microcomputer as the core devices. Its digital circuit block diagram is shown in Figure 1.

Figure 1 Digital circuit block diagram of the acoustic detection system

After the analog signal processed by the front end is sampled and converted by AD7865, an interrupt is given to the DSP. With the cooperation of the CPLD, the DSP reads the data of each channel and stores it in the off-chip SRAM data area. At the same time, the DSP performs digital filtering and spectrum analysis on the data. , so as to complete the localization function of the sound source target.

The exchange of target information between DSP and C8051F020 is realized by dual-port RAM, and finally RS-422 communication with the terminal is completed through MAX3485. In addition, the DSP realizes the gain control of the front-end analog circuit according to the processed result.

ADC design

The phase consistency of the sound in the passive sound detection system is very high, therefore, the AD7865, a 14-bit parallel output ADC with simultaneous sampling and holding function, is used in the design. In this design, the 6-channel sound source target signal processed by amplification and filtering realizes A/D conversion through two pieces of AD7865. In this paper, the output signal of the DSP timer is used as the start sampling signal of the ADC. After the sampling conversion is completed, an interrupt is given to the DSP through the BUSY signal of the ADC, and then the DSP enters the interrupt handler to read the A/D data, while the read and write signals and the ADC The chip selection signal is completed by the logical combination of the read and write signals and address signals of the DSP by the CPLD.

DSP and peripheral circuit design

The main function of DSP is to complete the automatic gain control of the front-end analog signal according to the amplitude of the collected digital signal. The data is subjected to operations such as digital filtering, fast FFT transformation and orthogonal transformation, and then completes operations such as positioning and identification of the target; through the dual-port RAM, the communication with the single-chip microcomputer and the timing start of the ADC are completed.

DSP peripheral circuits include program boot area Flash, program operation area SRAM, data exchange area dual-port RAM and gain control. Flash uses AMD29LV040B with a capacity of 1M*8b to form a code storage space; SRAM uses an SRAM memory CY7C1049-CV33 with a capacity of 512K*8b, and uses 4 chips in the circuit for bit expansion, thus forming a 512K*32-bit program running space; The dual-port RAM is 2K*8-bit IDT71V321; and the gain control is realized by using an 8-bit CMOS latch.

TMS320VC33-150 has four external interrupts, all of which can be used as BootLoader interrupts, so BootLoader prefers high-priority interrupts, otherwise it may fail to load the program when it is powered on offline. Because after the power-on reset, the DSP executes the resident program and searches for the BootLoader storage area according to the interrupt level. If the interrupt higher than the BootLoader interrupt is not invalidated, the DSP will search for the BootLoader storage area according to the high priority, thus causing the program Loading failed.

In addition, in the design process, for some important signals such as #RDY, #HOLD, EDGEMODE, MCBL/#MP, #SHZ, etc., according to the specific design, refer to the data sheet to give pull-up or pull-down processing accordingly. During the debugging process of this design, because the #HOLD signal is not processed, the program cannot be downloaded online, and finally it is solved by pulling it high.

Table 1 Interrupt number and program load address correspondence table

Figure 2 DSP software program design flow chart

logic control

In this design, Altera’s EPM7128AETC100-10 is used to realize the timing management and logic control functions of the entire circuit system, including ADC control function module, memory read and write timing control module, communication interface timing control module and gain control. And according to DSP external memory address space decoding to generate chip select signal and read and write timing. In this design, Quartus Ⅱ is used to complete the logic control simulation.

Microcontroller circuit

The C8051F020 single-chip microcomputer is a fully integrated mixed-signal system-level MCU. In addition to the digital peripheral components of the standard 8051 single-chip microcomputer, the chip also integrates analog components and other digital peripherals and functional components commonly used in data acquisition and control systems.

In this design, the serial port of C8051F020 is used to realize the RS-422 asynchronous serial communication with the computer terminal, and the baud rate is 19.2Kbps; the real-time exchange of the sound source target data of the DSP and the single-chip microcomputer is completed by using the dual-port RAM.

When designing the single-chip microcomputer circuit, in order to ensure the reliability of the power-on reset circuit, basic RC circuits and special monitoring integrated circuits such as MAX708T can be used, and the MODEN VDD monitor function should be fully utilized.

Auxiliary circuit

DSP software design

DSP software flow

The whole software is based on interrupt mode. The DSP software design includes ADC conversion start, data acquisition, interrupt service routine, digital filtering of sound source signal, fast FFT and orthogonal transformation, and MUSIC algorithm to obtain high-resolution spatial sound intensity distribution through spectrum analysis. The DSP software flow of the sound detection system is shown in Figure 2.

The DSP software workflow is: after the system is powered on and reset, load the program file of the external Flash to the external SRAM program area, and the DSP runs after initializing each part. The program always queries the interrupt signal of the ADC, and enters the interrupt service routine after obtaining the interrupt of the ADC. The collected data is stored in the external SRAM data area, and then the detection and positioning program is called to obtain the position and other parameters of the sound target, and write to the external dual-port RAM. , which is read by the single-chip microcomputer and sent to the computer terminal for fusion and rendezvous.

DSP program BootLoader

TMS320VC33-150 has two working modes, the choice of working mode is decided by MCBL/MP pin. In this design, by pulling up the MCBL/MP pin to a high level, the DSP works in the microcomputer/boot loading mode or the external memory loading mode. After the Reset signal changes from low level to high level, TMS320VC32-150 first checks the level of the external interrupt input line to decide where to start the boot program. The relationship between the interrupt number and the corresponding start boot address is shown in Table 1. . The BOOT2 method is used in this design, that is, after the DSP reset signal changes from low to high, the DSP starts to load the program from the external storage address 400000H.

It should be noted that when using the external memory loading method, the loader must contain the data bus width (8-bit, 16-bit or 32-bit) of the external memory, the length of the program code, the entry address of the program execution and the number of wait states of the memory.

In the process of loading the successfully debugged program into Flash, the method adopted in this article is: by writing a *.cmd conversion file, and then using HEX30.EXE to convert the *.out file into a *.hex file. And burn the generated *.hex file into Flash. Of course, the method of online programming can also be used.

Epilogue

The digital circuit design of the acoustic detection system based on TMS320VC33-150 makes full use of the powerful floating-point computing capability of TMS320VC33-150, and completes the algorithm processing of sound source target detection and positioning. At the same time, the logic control function of CPLD and the abundant peripheral resources of MCU are fully utilized, and the DSP algorithm and interrupt service routine flow are designed. The system has been debugged and fully field tested. The results show that the system works stably and all the indicators basically meet the requirements.