Design scheme of ARM/DSP multi-computer I2C communication based on Linux operating system

introduction

In many embedded control systems, the system not only needs to complete a large amount of information collection and complex algorithms, but also realize precise control functions. The ARM9 microcontroller running the embedded Linux operating system is used to complete the signal acquisition and realize the upper-layer control algorithm, and send the upper-layer algorithm to the DSP chip to obtain the control parameters. The DSP chip realizes accurate and reliable closed-loop control according to the obtained parameters and the lower-layer control algorithm. .

1 Multi-machine system composition

The multi-machine control system takes ARM9 microcontroller s3c2440 as the core, and uses I2C bus to mount multiple DSP chips TMS320F28015 as co-controllers, which constitute the core of the entire control system.

1.1 Introduction to S3C2440 and TMS320F28015

Samsung’s processor S3C2440 is a 32-bit microcontroller integrated with ARM’s ARM920T processor core. It is rich in resources, with independent 16 KB instruction Cache and 16 KB data Cache, and the highest frequency can reach 400 MHz. It has 130 general-purpose I/Os, 24 external interrupt sources and abundant external interfaces can realize various functions, including I2C bus interface supporting multi-master function, 3-way URAT, 2-way SPI, camera interface, etc.

TMS320F28015 (hereinafter referred to as F28015) is a 32-bit processor of TI Company. It has powerful control and signal processing capabilities and can realize complex control algorithms. On-chip peripherals such as Flash memory, I2C bus module, fast A/D converter, enhanced CAN bus module, event manager, quadrature encoding circuit interface and multi-channel buffer serial port are integrated. This integration can easily realize functions extension. At the same time, fast interrupt response enables it to protect critical registers and respond to external asynchronous events quickly (with smaller interrupt latency).

1.2 I2C bus interface

The I2C bus is a serial bus used for connection between IC devices. It uses SDA (data line) and SCL (clock line) to connect each device or module with an I2C bus interface. The serial 8-bit bidirectional data transfer rate can reach 100 kb/s in standard mode and 400 kb/s in fast mode. Multiple microcontrollers can be easily connected together through the I2C bus interface to form a system, and Each device is identified by address. This kind of bus structure has few connection lines and connection pins, the bus between devices is simple, and the structure is compact. Therefore, the cost of forming the system is low, and adding devices on the bus will not affect the normal operation of the system. All I2C bus devices share a set of buses, so the system modification and scalability are good.

The bus must be controlled by a host (usually a microcontroller), which generates the serial clock (SCL) to control the data transfers on the bus and to generate start and stop conditions. The data state on the SDA line can only be changed during periods when SCL is low. During periods when SCL is high, changes in the state of SDA are used to indicate start and stop conditions. The I2C bus start and stop timings are shown in Figure 1.

Figure 1 I2C bus start and stop timing

1.3 Hardware circuit

Both S3C2440 and F28015 integrate the I2C bus module, support multi-master I2C bus serial interface, and can be easily connected to the I2C bus. Therefore, the design of the I2C bus interface circuit between the two becomes very simple, as long as the corresponding pins of the two, I2C_CLK (corresponding to the SCL line in the I2C bus) and I2C_SDA (corresponding to the DATA line in the I2C bus) are connected. Can. The hardware interface circuit of S3C2440 and TMS320F28015 is shown in Figure 2.

Figure 2 Hardware interface of S3C2440 and TMS320F28015

The PA55 and PA56 pins of the circuit S3C2440 correspond to I2C_SDA and I2C_CLK respectively, and the GPIO32 and GPIO33 of the F28015 can also be reused as I2C_SDA and I2C_CLK respectively. Considering that the impedance mismatch and other factors will affect the bus data transmission effect, the two chips are combined When the I2C_DATA and I2C_CLK pins are directly connected, connect a small resistor in series on the direct connection line.

I2C_SDA and I2C_CLK are bidirectional circuits and must both be connected to a positive supply voltage through a current source or pull-up resistor. Since the output high levels of S3C2440 and F28015 are both 3.3 V, the I2C_SDA and I2C_CLK buses are connected to the 3.3 V VCC power supply through a pull-up resistor during hardware design.

2 ARM and DSP communication software design

As the main controller, the ARM microcontroller running the Linux operating system has significant advantages in data management and multi-task scheduling, and can well organize the data collected by peripheral devices; it mainly realizes the overall control of the system, and uses the bus The device driver controls the I2C bus module, and realizes data transmission and reception to the lower-level DSP mounted on the I2C bus through host addressing. In order to ensure the real-time nature of data communication, F28015 realizes data reception and transmission by way of interrupt response.

2.1 I2C bus driver design of embedded Linux on ARM9 platform

2.1.1 I2C bus read and write timing

The ARM9 microcontroller, as the master, writes data to the slave DSP, first sends a start signal to the slave, then sends a 7-bit slave address and a 1-bit write flag, and then waits for the slave’s response signal. After receiving the response signal, the master sends data to the slave and waits for the response signal again. When the host receives the acknowledgment signal, it sends the data again. After that, the master waits for the response signal from the slave, so until the data transmission is completed, the master sends a stop signal. The I2C bus write data frame format is shown in Figure 3.

Figure 3 I2C bus write data frame format

Reading data in master mode means reading one or more bytes of data from a specified location at a time. The master first sends a start signal to the slave, then sends a 7-bit slave address and a 1-bit read flag, and waits for the slave to respond. After receiving the response signal from the slave, the master is ready to receive the data sent by the slave, and sends a response signal after receiving it, so that until the data reception is completed, the master sends a stop signal. Figure 4 shows the I2C bus read data frame format.

Figure 4 I2C bus read data frame format

2.1.2 Overview of I2C bus driver under Linux

The I2C bus driver of the Linux system adopts an architectural design, including the I2C bus adapter driver and the I2C bus device driver. The bus driver realizes the control of the I2C bus adapter (I2C bus module of S3C2440), and the device driver realizes the read and write control of the specific device (I2C bus module of F28015). Figure 5 shows the overall drive framework, which can be divided into three levels:

① I2C framework. The i2c.h and i2ccore.c in the kernel are the main body of the I2C bus framework, providing the definition of the core data structure, the registration and deregistration management of the I2C bus adapter driver and the device driver, and the code of the upper layer of the I2C bus communication method that has nothing to do with the specific adapter. , upper-level code to detect device address, etc. i2cdev.c is used to create the device node of the I2C bus adapter, providing I2C bus device access methods, etc.

② I2C bus adapter driver. Define the data structure describing the specific I2C bus adapter, and implement the I2C bus communication method on the specific I2C bus adapter.

③ I2C bus device driver. Define the data structure that describes the specific device, realize the registration of the device with the help of the related functions of the I2C bus frame, and provide the upper-level application programming interface for the user.

Figure 5 Overall drive framework

The main data structures in Linux’s I2C bus driver framework include: i2c_driver, i2c_client, i2c_adapter and i2c_algorithm, which are defined in the i2c.h header file in the kernel. i2c_adapter corresponds to a physical adapter, and i2c_algorithm corresponds to a set of communication methods used to provide communication functions for the adapter. The key function master_xfer() in i2c_algorithm is used to generate the signals required by the I2C bus access cycle, in units of i2c_msg (ie, I2C bus messages). The prototype of the structure is as follows:

struct i2c_msg{
_ _u16 addr;/*device address*/
_ _u16 flags; /*flags*/
_ _u16 len;/*message length*/
_ _u8 *buf;/*Message data*/
};

i2c_driver corresponds to a set of driver methods and is a data structure for auxiliary functions. i2c_client corresponds to the real physical device, and each I2C bus device needs an i2c_client to describe. The relationship between i2c_adapter and i2c_client is consistent with the relationship between adapters and devices in the I2C bus hardware system, that is, i2c_client is attached to i2c_adapter.

Figure 6 Device driver module loading process

The i2c_dev.c file in the drivers directory in the Linux kernel source code is a general I2C bus device driver file that provides open(), write(), read), ioctl() and close() for applications to operate interfaces to access device. The application layer can use these interfaces to access the storage space or registers of the I2C bus device attached to the adapter, and control the working mode of the I2C bus device.

2.1.3 I2C bus driver of S3C2440

The I2C bus controller inside the device driver S3C2440 implements communication control through 4 registers, which are the I2C control register (I2CCON), the I2C status register (I2CSTAT), the I2C transceiver data shift register (I2CDS), and the I2C address register (I2CADD). ).

According to the requirements of the I2C bus framework in Linux, the I2C bus driver design of S3C2440 mainly completes the following tasks: design the i2c_adapter_s3c_init() template loading function and the corresponding i2c_adapter_s3c_exit() template unloading function; design the i2c_adapter_s3c_xfer() template S3C2440 adapter communication method function.

i2c_adapter_s3c_init() realizes the platform registration of the bus driver by registering the s3c2440_i2c_driver structure. The s3c2440_i2c_driver structure contains the probe() function, remove() function, resume() function pointer and other information of the specific adapter. code show as below:

static int _ _init i2c_adap_s3c_init() {
int ret;
ret=platform_driver_regisiter(&s3c2440_i2c_driver); //register platform_driver structure
if(ret==0){//Registration failed
ret = platform_driver_regisiter(&s3c2440_i2c_driver);
if(ret)
platform_driver_unregisiter(&s3c2440_i2c_driver);
}
return ret;
}
static struct platform_driver s3c2440_i2c_driver={
.probe=s3c24xx_i2c_probe,
.remove=s3c24xx_i2c_remove,
.resume=s3c24xx_i2c_resume,
.driver={
.owner=THIS MODULE,
.name=”s3c2440i2c”,
},
} ;

After completing the registration of the I2C bus adapter driver of the S3C2440, the specific device driver can be registered on the bus platform to realize the I2C bus data communication. The i2c_dev.c file is a general I2C bus device driver file provided by the kernel source code. A device file with a major device number of 89 is generated for each I2C bus adapter. The device driver module loading process is shown in Figure 6. After loading, the driver provides i2cdev_read(), i2cdev_write(), and i2cdev_ioctl() functions to correspond to the read(), write(), and ioctl() functions of user space for users to use. Users can realize the read and write functions of I2C bus data through these interface functions.

2.2 DSP data receiving interrupt program design

Figure 7 I2C bus interrupt service routine flow

By configuring the I2C module register of the F28015, the I2C module is set to work as a slave, and at the same time, the I2C bus interrupt response program is used to receive and send data on the bus, and then complete data communication. After the F28015 generates an I2C bus interrupt, it executes the interrupt service routine. Figure 7 shows the flow of the I2C bus interrupt service routine.

The interrupt service routine obtains the interrupt type code by querying the status register (I2CSTR) flag bit, and then calls the corresponding subroutine to complete the data reception and transmission. code show as below:

interrupt void i2c_int1a_isr(void) {//Interrupt response function of I2CA
Uint16 IntSource;//Read the interrupt code
IntSource=I2caRegs.I2CISRC.bit.INTCODE & 0x7;//I2CA interrupt source, read last 3 bits
switch(IntSource){//Determine the relevant receiving and sending strategies according to the interrupt source
case I2C_NO_ISRC://=0
case I2C_ARB_ISRC://=1
case I2C_NACK_ISRC: //=2
case I2C_ARDY_ISRC: //=3
case I2C_SCD_ISRC://=6
case I2C_AAS_ISRC://=7
break;
case I2C_RX_ISRC://=4, receive data is ready
DataReceive();//Call the data receiving sub-function to receive data
break;
case I2C_TX_ISRC://=5, send data is ready
DataTransmit();//Call the data sending sub-function to receive data
break;
default:
asm(“ESTOP0”); //Invalid data, stop
}
PieCtrlRegs.PIEACK.all=PIEACK_GROUP8;
}

The data receiving subroutine and the data sending subroutine in the F28015 are called according to different status codes in the interrupt service routine of the I2C bus, and they are the core part of the entire communication program. The flow of the data receiving subroutine and the data sending subroutine is shown in Figure 8.

Figure 8 Data receiving and sending subroutines

3 Test results

Load the I2C bus driver and device driver compiled into a module into the S3C2440 platform running the Linux operating system through the NFS file system (load the bus driver first), and then program the F28015 test program into RAM. Run F28015 to wait for the data on the I2C bus, and then execute the I2C bus test program in the Linux system. The test results show that the chip completes data communication through the I2C bus interface, and has good real-time performance and reliability.

4 Conclusion

The design uses I2C bus to realize real-time and reliable data communication between ARM9 microcontroller and DSP chip. The ARM9 microcontroller combines the Linux operating system as the upper-level control core, and the DSP chip implements the lower-level control algorithm, which can give full play to the advantages of the ARM9 microcontroller in data acquisition and task management, as well as the advantages of the DSP chip in algorithm implementation and underlying control.