FPGA-Based Cadence Protium S1 Prototyping Platform

“IoT spans multiple application domains, and the requirements of design teams can vary widely depending on the end application domain. Power, performance and cost are priorities in chip design, while application areas such as automotive and aerospace/defense also need to consider functional safety. In other areas, information security is a key or field-upgradeability requirement.

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IoT spans multiple application domains, and the requirements of design teams can vary widely depending on the end application domain. Power, performance and cost are priorities in chip design, while application areas such as automotive and aerospace/defense also need to consider functional safety. In other areas, information security is a key or field-upgradeability requirement.

Validation, prototyping and software development are common among these areas and design requirements. To allow for embedded software development, early verification techniques were often considered too slow, and abstractions using virtual platforms such as QEMU were sometimes inaccurate.

FPGA-based prototyping has long been the platform of choice for pre-chip software development. Similar to hardware emulation in tools like the Cadence Palladium Z1 enterprise emulation platform, it can scale execution performance from MHz to 100 MHz at a lower cost, allowing it to be handed off to more developers on the software team.

Traditionally, the hurdle for FPGA-based prototypes has been its start-up process, which sometimes takes months to make it available to software developers. The reason is that the ASIC design needs to be remapped from its actual chip into the structure provided by the FPGA, which requires remapping various parts of the design.

Prototype verification process

For starters, the memory in the ASIC needs to be mapped to resources available in the FPGA, or to a daughter card with specific additional memory (eg DDR). Dealing with clocks for ASICs can be a nightmare, with 10+ clocks synchronizing in more complex designs on PCBs and FPGAs. Design partitioning across multiple FPGAs is not an easy task, often requiring multiplexing of multiple signals on the same pin using low-voltage differential signaling (LVDS) techniques.

Traditionally, larger companies have prototyping teams that specialize in the RTL version the design team is developing and map it into the FPGA. However, as design complexity increases, it becomes increasingly difficult to perform all of the above tasks.

With a Protium S1 FPGA-based prototyping platform, Cadence has redeveloped the prototyping process and focused on reducing prototyping time from months to weeks or even days. By achieving consistency between the Palladium Z1 simulation and the FPGA-based Protium S1 FPGA prototype, as well as reusing some front-end simulations for the prototype.

Complex manual memory modeling has been automated using memory models known from simulation; the compilation flow takes care of partitioning and clock synchronization between FPGAs. Netlists to be mapped into the FPGA fabric can be verified in simulation, saving valuable place and route time. Defects are found in FPGA-based prototypes approximately 5 times faster than simulation, thus facilitating better debugging capabilities of simulation.