“Compared with the C2000 of Gen-2, the C2000 Gen-3 adds a trigonometric function operation unit to further improve the operation capability, and provides more ADC Modules and window comparators to enhance the speed and flexibility of sampling and protection. At the same time, in terms of real-time communication, a new generation of fast serial communication interface Fast Serial Interface (FSI) has been introduced, which can support data transmission rates of up to 200Mbps in isolation.
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Author: Dylan You
Compared with the C2000 of Gen-2, the C2000 Gen-3 adds a trigonometric function operation unit to further improve the operation capability, and provides more ADC modules and window comparators to enhance the speed and flexibility of sampling and protection. At the same time, in terms of real-time communication, a new generation of fast serial communication interface Fast Serial Interface (FSI) has been introduced, which can support data transmission rates of up to 200Mbps in isolation.
This article mainly discusses the selection of ADC channels, the application of FSI interface, the consideration of 3.3V power supply selection, the configuration of GPIO port, and the connection and debugging of JTAG.
1. Input parasitic capacitance of ADC channel:
When we match the external signal to the ADC channel of the C2000, we often ignore the potential impact that the input model of the ADC may bring. The most obvious one is that there will be an input parasitic capacitance on each ADC channel, and ADC channels with large input parasitic capacitance are usually not suitable for high-frequency sampling signals. This is because larger input parasitic capacitances result in longer sampling windows, which in turn may affect the Computational power budget in the control loop. For more information, refer to the Choosing an Acquisition Window Duration chapter of the F28002X TRM.
For the C2000 of Gen-3’s F28002X, we can query the internal input parasitic capacitance of each ADC channel in Table 1 in the ADC Input Model chapter of the data sheet. Based on Table 1, ADCINA3/ADCINC5 channel is obviously not suitable for high-speed sampling signal regardless of whether the comparator is enabled or not, because its internal input parasitic capacitance reaches 71.4pF. For ADCINA0/ADCINC15, if the internal comparator is used, the sampling window and external sampling Circuit need to be carefully considered. For example: if we want to use a certain ADC channel to implement the OVP function, and we only have the ADCINA0/ADCINC15 channel left, then we can use the software code to implement the OVP function in the background task without using the internal comparison device. If we must implement the OVP function based on the CMPSS module, it is recommended to switch to other channels to the ADC.
Table 1: ADC Channel Parasitic Capacitance
2. FSI interface introduction:
The FSI interface is the latest high-speed and reliable fast serial interface introduced by Gen-3’s C2000. For communication application scenarios that require isolation, the FSI receiver module has a programmable Delay Line Control. By modifying the RX_DLY_LINE_CTRL register value of each line, the signal delay caused by system components (such as signal buffers and isolators, etc.) and the signal delay caused by board level (such as uneven wiring, etc.) are compensated, Finally, the integrity of the signal is guaranteed, and high-speed and reliable communication is realized. FSI is a point-to-point communication protocol, such as single-master/single-slave configuration, so FSI is mainly used in the following two scenarios:
• Two MCUs communicate directly
• Communication between boards, such as the two MCUs on the primary and secondary sides of the PSFB communicate through the isolation chip
The transmitting end (FSITX) and the receiving end (FSIRX) of the FSI interface are completely independent, and each port has its own independent register, clock and interrupt. An important difference from the IIC interface is that it can only be used as a communication transmission in a single direction. Based on Figure 1, each port of FSI has 3 signal lines, which are clock CLK, data line D0 and an additional data line D1. The extra data line D1 is used as a multi-line transmission to double the data transmission rate, and can also be used as a GPIO port. Therefore, in general, point-to-point FSI requires at least 4 signal lines. The maximum supported clock frequency of FSI is 50MHz, and the rising and falling edges of the clock can also be used as valid bits of data to determine. Therefore, theoretically, the transmission rate of up to 200Mbps can be achieved.
Figure 1: FSITX/RX Module Connection Diagram
In motor drives and digital power supplies, real-time communication between MCUs is becoming more and more common, and this also requires higher real-time communication performance. Because the FSI interface has programmable delay line control, it can ensure high-speed and reliable communication in isolated application scenarios, so it has more advantages than traditional communication interfaces such as UART, SPI and CAN.
F28002X FSI and IIC compatible GPIO port and isolation chip:
If we want to use F280025C 64pin as the secondary side MCU and the primary side MCU for FSI communication, in the stage of system debugging, engineers sometimes hope that the communication interface can be used as both FSI and IIC communication. At this time, some problems will be introduced. For example, IIC is two-way communication, while FSI is one-way. For F280025C 64pin, only the following GPIO ports can support both FSI and IIC:
• GPIO33 >> I2CA_SCL and FSIRXA_CLK
• GPIO8 >> I2CA_SCL and FSITXA_D1
• GPIO0 >> I2CA_SDA and FSIRXA_CLK
• GPIO32 >> I2CA_SDA and FSIRXA_D0
• GPIO10 >> I2CA_SDA and FSITXA_CLK
First, only GPIO32 is the data line that supports FSIRXA_D0. Secondly, only FSI and IIC of GPIO33 are used as clocks. So we recommend using GPIO32/33 as the data and clock lines of the receiver (RX).
In addition, when selecting an isolator, if we have clarified the communication direction, then as long as we maintain the data transmission direction of IIC and FSI, we can still use unidirectional isolators, such as ISO7742, to transmit data.
3.3V power supply chip selection small details:
Usually, when we select the corresponding pre-stage DC/DC or LDO according to the power supply VDDA/VDDIO of C2000, we will focus more on parameters such as output current capability, PSRR and voltage drop. Impact. For the reference DAC module of the C2000 internal CMPSS module, the system block diagram is as follows. If we choose VDDA as the reference voltage of COMPDAC, then any percentage change in VDDA will affect the output of COMPDAC. Therefore, for DC/DC in peak current control mode, it is recommended to use an LDO with 1% accuracy, such as TPS7A90.
Figure 2: Block Diagram of Reference DAC Section of C2000 CMPSS Module
4. GPIO port and external signal matching:
• Tri-state external signal. For example, when the external signal is Active, it needs to be pulled high, in the Sleep state, it needs to be pulled down, and the IDLE mode needs to be Floating. Then we have two ways to deal with it, the first is by setting the GPIO as an input and then disabling the pull-up, and the second is by setting the GPIO as an output and open drain while setting the GPIO level low. And this can be achieved through the GPAODR register in the C2000.
• Under certain circumstances, some digital ports, such as enabled, can be configured to analog ports if they are not enough to be pulled low at low level. Then, the judgment of high and low level is realized through the judgment of the analog quantity by the software, so as to realize the enabling and closing.
Alternatives when digital GPIO ports are not enough:
• Use the feedback voltage (digital signal on the primary side) originally used as a fan and other small devices as an analog GPIO port. Then, the high and low levels are judged based on the sampled voltage through the software code.
• If GPIO24 and GPIO32 of boot load are boot from flash, two GPIO ports can be saved. If it is boot from SCI and CAN, etc., it can be reused as other GPIO ports after the boot is completed.
5. JTAG interface connection and debugging:
Generally speaking, JTAG (IEEE Standard 1149.1-1990 Standard Test Access Port and Boundary Scan Architecture) has five pins: TMS/TDI/TDO/TCK/TRSTn. The three main functions are as follows:
• Download software to the MCU’s Flash
• Commissioning
• Boundary scan: access the signal logic state inside the chip and the chip pin state, etc.
Usually the debugging process for problems with the JTAG connection is as follows:
a) Power Good LED on: All TI C2000 development boards have LEDs to identify whether the power supply to the MCU is normal.
b) Check Device Manager: To use the JTAG emulator to communicate with the PC, we first need to install the driver file. Usually we have specific details when installing CCS. To verify that the driver was successfully installed, connect the JTAG emulator to the PC and power it up. Then navigate to the USB emulator in the PC’s Control Panel >> Device Manger.
Figure 3: Device Manager Driver Confirmation
c) Check whether the TRSTn signal of MCU JTAG is pulled high: If TRSTn does not change state during the CCS connection process, then it is necessary to verify whether the emulator is configured normally.
d) Check the Target Configuration: The Target Configuration File (.ccxml) will contain all relevant information about connecting the Target device and the type of JTAG emulator. Click “View” in CCS, then click Target Configuration, find the .ccxml file under User Defined, and the New Target Configuration interface will be displayed as shown below. Select the appropriate Devices in the figure below, keep the configuration, and then click Test Connection to test whether the connection is normal.
Figure 4: Target Configuration confirms the connection is normal
e) Start CCS debugging.
f) Check the XRSn state: If the state of XRSn is low or pulses from low to high to low, it may be caused by a variety of factors. For example, if it’s a low-to-high-to-low pulse, it could be a watchdog-induced restart. If it is always low, Brown Out Rest (BOR) may be caused by power supply or other reasons on the PCB.
g) Check Boot Mode: If the default Bootload port of GPIO24 and GPIO32 is used, then refer to chapter 3 in TRM of F28002X to check the pins of GPIO24 and GPIO32 to confirm whether it is in the expected Boot load mode.
h) Check VREG/Clock/System Clock: Measure and confirm that the JTAG clock and crystal oscillator are in accordance with the data sheet. Measure and confirm whether the power supply is running outside the recommended voltage value, causing problems such as BOR.
The Links: LQ104S1DG31 G104AGE-L02