General layout considerations for MOSFETs

Power MOSFETs are essential parts of the power electronics industry for various applications. However, the practical implementation of these devices is not easy for high frequency applications. At high frequency applications, these FETs are subjected to various losses that are dissipated at each cycle for reliable operation. Apart from the thermal considerations, these FETs are also prone to false triggering because of the parasitic generated from the leads and the traces of the PCB. Hence, layout considerations during the design process are important.

Leaded packages have higher parasitic inductances than (surface mounted device) SMD packages, and the internal geometry of the drain and source connections determines how much inductance is present in an SMD package. Different FET packages have different parasitic inductances generated by its leads between the die and the terminals. Measures have to be taken while designing high current applications to ensure efficient heat transfer from the package to PCB to ambient apart from preventing EMI issues.

In order to achieve acceptable performance, prevent potential EMI problems, and switch high currents in hard commutation, it is necessary to use an SMD package with the lowest feasible inductance in combination with a well-designed PCB. When designing a PCB for a power application, it is recommended to adopt the manufacturer’s suggested device footprint and to observe all handling and soldering instructions.

Stray inductance in power switching circuits increases the amplitude and energy of overvoltage transients, making it necessary to reduce switching speed to avoid avalanching. Rapid variations in current can cause transients. The parasitic inductor opposes the change in current and the induced voltage across the parasitic inductor is proportional to the rapid variations in current (dI/dt) as shown in Equation

1.  Vds= (Ls)dI/dt

Equation 1. Induced voltage across the parasitic inductor

Here, Ls (source inductance) is formed by the loop created between the current source (e.g., bus capacitor in half-bridge or inverter topologies) and the switching FETs. Long traces and larger loop areas produce radiated EMI. Positioning the MOSFETs and the DC bus decoupling capacitor as closely as possible reduces the loop inductance. The return current path should be placed directly underneath the current path, starting at the decoupling capacitor and passing through the MOSFETs to create tight coupling. This is accomplished by using two or more layers of copper in the PCB. A power ground plane is frequently used as the return path. In a multi-layer PCB, it is typical to reserve one or more copper layers to create this.

Figure 1. Cross sectional layout of the PCB

Signal or digital grounds and power grounds should be kept apart to prevent ‘ground bounce’, which can effect sensitive control circuitry. The best ground connection for power and signal should be the decoupling capacitor ground connection.

The dashed red line indicates a cross-section of a simplified path that uses the top and bottom copper layers to create a tight current loop. The two layers are connected with multiple vias, which are also used to transfer heat to the bottom side of the board. While designing the layout including the gate driver and the MOSFET, consider the following parameters:

• Ground plane: Power tracks in the design, often utilize ground or the return path in their schematic. For the power paths if the current ratings are usually higher than the control traces. It is recommended to have a common copper plane in the schematic instead of providing multiple tracks, as this aids in providing shielding against noise. It also helps in providing the better heat dissipation and can act as a heatsink for the PCB. Hence suitable polygon thickness can be added on the PCB based on the current ratings of the PCB.
• Bypass capacitor: In order to filter the ripple components of a power supply, the bypass capacitors are usually provided at the switching gate driver. The connection of the bypass capacitor between the supply pin and the ground should be as close as possible. The traces should be placed under the package in order to achieve the shortest path, and in this way the magnetic fields between the two traces can also be cancelled.
• Trace between the MOSFET and gate driver: Suitable placement of the driver and FETs is important to avoid ringing and EMI issues during the operation. These issues are generated by the parasitic which in turn is generated by the traces and polygons on the PCB. To reduce such risks, ground polygons can be made common which can interfere with the adjacent connections and can impact the performance. The length of the traces between the driver and the switch has to be kept minimum in order to reduce the parasitic inductance generated and to prevent unwanted switching at high frequencies and currents.
• Selecting the right package: The FETs with the same technology and voltage class can be offered in several packages to meet different demands from the end application. These packages can have different parasitic, especially the inductance due to their internal connections between the die and leads, which could be a bond wire or clip depending on the current rating of the FET. The parasitic is also proportional to the length of the leads (for through hole packages) or pins (for surface mount packages). These parasitic can also affect the operating frequency limits especially at high frequency operations. Hence, selecting the right package is important during the designing process.