High-efficiency design of high-voltage gallium nitride transistor gate driver optimization

In the field of power electronics, there has been a significant increase in demand for high-voltage (HV) gallium nitride (GaN) transistors in recent years. Compared to traditional silicon-based devices, high-voltage gallium nitride transistors offer significant advantages, such as lower conduction and switching losses, higher power density, and improved efficiency. These features support numerous applications across renewable energy systems, electric vehicles, industrial motor drives, aerospace technology, and more.

In a virtual tutorial at the 2023 PowerUp Expo, Eric Persson, Senior Chief Engineer at Infineon Technologies, pointed out that 600/650V GaN transistors are referred to as high-voltage GaN transistors. GaN has several advantages over similar Rds(ON) silicon or silicon carbide MOSFETs:

1. No reverse recovery effect caused by minority carriers, facilitating hard switching.
2. Lower gate charge due to lower input capacitance and threshold voltage.
3. Low and linear output capacitance, reducing switching losses even in soft-switching topologies.
4. No avalanche characteristics, making it more robust against high-voltage events like lightning transients.

However, most gate driver circuits for GaN transistors typically use silicon-based chips, and this hybrid solution of silicon chip + GaN transistor introduces more parasitic inductance issues. The sources of these inductances can be wires or on-board traces, which are more prevalent in high-frequency switching scenarios. Therefore, to fully harness the potential of GaN transistors, it becomes crucial to design gate drivers that ensure reliable and high-performance operation. Well-designed gate drivers, consistent with those used by Infineon for Power Factor Correction (PFC) units, can mitigate various issues like high switching losses, larger layout size, keeping EMI within limits, and operating at lower efficiency at higher frequencies. It also simplifies thermal management and ensures a reliable and competitive system cost. This article explores one of the general approaches to designing gate drivers and the key design techniques used by Infineon to develop optimized gate drivers for high-voltage gallium nitride transistors.

Integrated Gate Drivers for Gallium Nitride Power Devices

To develop an integrated gate driver, a group of researchers implemented enhancement (E)-mode GaN power switches and GaN-based single-chip integrated gate drivers on a commercial 650V silicon-based GaN platform. This integration eliminates additional processing steps and simplifies the manufacturing process. The gate driver utilizes low-voltage E/D-mode HEMTs to form the gate driver circuit, achieving precise control by reshaping the transmission input PWM signal.

To ensure reliable and efficient operation, several design factors were considered. The gate driver voltage was set at 6-7V to ensure full conduction of the power switch. The gate charge required to turn on the GaN power transistor (approximately ~2 nC) is significantly lower than that of silicon power transistors, thereby improving efficiency.

In traditional designs, slower switching speeds were observed due to the charging process of the power switch. To overcome this limitation, a charge pump circuit was introduced in the gate driver. This approach ensures a constant voltage (VGS) in the pull-up charging transistor, thereby improving the charging speed and reducing gate stress. The new Gen-II gate driver design offers higher driving capability, rail-to-rail output, and efficient GaN power device turn-on, as shown in Figure 1.

[Figure 1: Comparison of Gen-1 and Gen-2 GaN power device circuits (source: [1])]

The chip characteristics of the gate driver demonstrate its ability to efficiently drive a 650V/130mΩ GaN power transistor. The static current of the gate driver is approximately 6mA, minimizing static power consumption. Propagation delay measurements indicate fast turn-on and turn-off times of only 2.9ns and 1.7ns, respectively, due to the lateral GaN power device’s superior current density and smaller intrinsic capacitance.

Negative Gate Bias to Prevent Overcharging of Gate-Source Capacitance

During the turn-on process, such as from 0V to 50V, a peak current is injected into the gate node within a short period, which can cause charging of the gate-source capacitance and unnecessary turn-on of the high-side transistor. Persson explained how applying a negative bias to the gate instead of zero voltage prevents charging of the gate-source capacitance, ensuring that the high-side transistor remains in the off state. For 650V high-voltage gallium nitride transistors, a negative bias of approximately -2.5V to -3V is sufficient to achieve the desired result and prevent overcharging.

A simple DC-DC converter can be used to implement this gate driver. The converter, controlled by an adjustable duty cycle oscillator or microcontroller, provides a separate power supply with the required negative bias. Adjusting the duty cycle allows control of the negative bias’s magnitude. The DC-DC converter employs a capacitive coupling approach, providing a simple solution without the need for additional voltage regulators or complex designs. The configuration of such a gate driver with a DC-DC converter is shown in Figure 2, demonstrating Infineon’s compact design that can be mounted on a small card. This configuration enables positive and negative biases for the gate driver of both high-side and low-side transistors. Providing sufficient negative bias effectively prevents false turn-on and ensures reliable operation. Infineon’s sub-card can deliver up to 3.5KW of power, with PFC unit peak efficiency reaching around 99.3% and utilizing isolation drivers for high-side and low-side.

[Figure 2: Schematic and physical design of the DC-DC converter with negative bias supply (source: Infineon Technologies)]

It should be noted that providing more negative gate bias may increase margins and prevent false turn-on. However, it will also increase the diode voltage drop during the third-quadrant conduction. Thus, a balance must be struck between providing sufficient negative bias and maintaining efficient operation.

Minimizing Power Loop Inductance is the Final Step in Designing GaN Gate Drivers

Persson emphasized the use of surface-mount packages to minimize power loop inductance, as through-hole components would need to operate at lower frequencies to mitigate overshooting of instantaneous inductance voltage. This limits GaN’s high-frequency capabilities, making surface-mount packages the preferred choice, as seen in Infineon’s sub-card design in Figure 2. Another approach is to pay attention to the direction of current flow to maximize the return current mutual inductance.

The gate driver current loop shares a common inductance path with the main current, which can be in the range of several tens of amperes, and experiences changing current (dI/dt) through the path’s inductance. This changing current induces voltage at the ends of the inductance, which can affect the applied gate voltage and slow down turn-on and turn-off times. It may also cause oscillation issues and impact the overall performance of the system. Therefore, careful design of the circuit layout and wiring can create a return path that maximizes mutual inductance and assists in designing efficient gate drivers for GaN power devices.