How to implement FPGA configuration through PCIE protocol?

CvP (Configuration via Protocol) is a solution for FPGA configuration through protocols. Arria® V, Cyclone® V, Stratix® V, Arria® 10, Cyclone® 10 GX, Stratix® 10, and Agilex™ all support this function, but The supported modes vary. The protocol used today is PCI Express® (PCIe).

The CvP configuration file is split into two, one is the peripheral image and the other is the core image.

•Periphery image (*.periph.jic) contains GPIOs, I/Oregisters, GCLK, QCLK, RCLK clock networks, PLLs, transceivers, memory PHY interfaces, and hard IP such as PCIe hard. This part cannot be changed and updated. The Periphery image is stored in the FPGA configuration chip and loaded when powered on.

• Core image (*.core.rbf) contains the logic section configured by configuration RAM (CRAM), including LABs, DSP, and embedded memory. After the FPGA device is powered on, the host side downloads and configures the core image into the FPGA through the used protocol (here, PCIe).

2. CvP system structure

The CvP system consists of three parts: FPGA, PCIehost, and FPGA configuration device. Figure 1.

Figure 1 CvP system structure diagram

(1) The configuration device and the FPGA are interconnected through the traditional configuration interface. For V series and Arria10 devices, any configuration is supported, such as AS, PS, or FPP. For Stratix10, Active Serial x4 (fast mode) or Avalon Streaming (Avalon-ST) x8 can be used. For the Agilex family of devices, only Active Serial x4 (fast mode) can be used.

(2) For V series, Arria10, Stratix10, Cyclone10GX, only the PCIe hard core on the left side of the bottom of the device supports the CvP function, and other PCIe hard cores can be used for regular functions. For the Agilex series, the PCIe hard cores on the left all support the CvP function. In the hardware design stage, it is necessary to confirm which PCIe is used for CvP. Once determined, only this PCIe hard core can be used as an Endpoint to enable the CvP function. Other PCIe hard cores can no longer be used for this purpose, but can be used as conventional PCIe interfaces.

(3) Other PCIe hard cores can be used as conventional PCIe interfaces.

3. CvP Value

• Since only peripheral logic needs to be stored, FPGA configuration devices can choose small-capacity devices to reduce costs.

• Coreimage exists on the host side to improve the security of core logic.

• For devices that support CvP Update Mode, dynamic core logic updates can be supported without requiring a system power cycle.

• A simple software configuration model is provided on the host side.

4. CvP Mode

CvP has two modes: CvP Initialization mode and CvP Update mode.

4.1 CvP Initialization Mode

The FPGA loads the peripheral image on the configuration chip when it is powered on, and successfully configures its PCIe interface within the enumeration time of 100ms, so that the host can correctly enumerate the PCIe device. After the host is started, the FPGA core logic is configured through the PCIe link.

Advantages of CvP Initialization Mode:

• Ensure that the FPGA PCIe device meets the enumeration time.

• FPGA configuration devices can choose small-capacity devices to reduce costs.

• Ensure the security of the core logic on the host side.

4.2 CvP Update Mode

When the FPGA enters the user mode, other logics except the CvP PCIe core are reconfigured through CvP. At this time, the CvP PCIe can be used for both conventional PCIe and FPGA core logic updates. In order to use this mode, it is necessary to refer to the Partition process to design the project into Modules Partition and Logic Lock, so as to reuse the device peripherals and ensure that the peripheral image remains unchanged.

Consider using this mode when you have the following needs:

• Core logic needs to be updated.

• Update devices based on feature releases.

4.3 Modes Supported by Different Device Families

As mentioned earlier, ArriaV, CycloneV, StratixV, Arria10, Cyclone10GX, Stratix10, and Agilex all support CvP, but the modes supported by different series of devices are different, as shown in Table 1. Among them, Agilex only supports InitializationMode, as shown in Table 2.

Table 1 Modes Supported by Different Device Families

Table 2 Modes supported by Agilex series

5. CvP Initialization mode implementation process and precautions

Use the Stratix V development board to implement the process and precautions of CvP Initialization mode.

• Board: Stratix-VGX Dev Kit (PCIe board), PCIe Gen1x8.

• Host: 64-bit Windows7 operating system.

• Quartus version: QuartusII 64-Bit Version 14.1.0 Build 186

5.1 Implementation process

1. Build a project with PCIe IP, here the Example design of S5PCIe is used.

2. Open the GUI of PCIe IP in the project and check “Enable configuration via the PCIe link”.

3. In Assignments => Device => Device and Pin Options => Configuration, select the configuration mode of the FPGA as Active Serial x4 (and set MSEL).

In Assignments => Device => Device and Pin Options => CvPSettings, select configuration via protocol as Core initialization.

4. Assign pins according to the development board and compile the project to generate cvp_example.sof.

5. Split the generated cvp_example.sof, open File => Convert Programming Files, and set the Programmingfile type to JTAG Indirect Configuration File (.jic). Add cvp_example.sof, check Create Memory Map File and Create CvP files. After clicking Generate, cvp_example.sof is split into two parts, cvp_example.periph.jic and cvp_example.core.rbf.

6. Turn off the host, connect the PCIE board to JTAG, insert it into the PCIe slot of the host, and then power on the host again. At this time, the PCIE board is powered by the PCIE slot. Open Quartus II Programmer, click Auto Detect to scan the JTAG chain, select FPGA, click ChangeFile, select the previously generated cvp_example.periph.jic file, and program it into EPCQ256.

7. Reboot the host to enumerate PCIe devices. At this time, the PCIE board that has loaded cvp_example.periph.jic will be recognized by the system as a PCIE device. According to the PCIe IP settings, check the PCIe device with DeviceID E001 and Vendor ID 1172 on the host side.

A free software “RW C Read & Write Utility” can be downloaded at this time. Find the PCIe device with Device ID E001 and Vendor ID 1172.

8. Use quartus_cvp on the host to load the core logic part cvp_example.core.rbf for the identified PCIe card (Device ID is E001, VendorID is 1172). Open Windows CMD and change the path to where cvp_example.core.rbf is located.

Enter the following command and press Enter:

• quartus_cvp –vid=1172 –did=e001 cvp_example.core.rbf

If the command is successfully executed, the following interface will appear, indicating that the core logic has been successfully loaded into the FPGA. At this time, the FPGA enters usermode and can work correctly.

5.2 Notes

Jungo WinDriver is required to run quartus_cvp.