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In-depth analysis of IGBT gate driver precautions.

Posted on: 07/15/2023

The structure of an IGBT transistor is much more complex compared to MOSFET or Bipolar Junction Transistor (BJT). It combines the characteristics of both devices and has three terminals: a gate, a collector, and an emitter. In terms of gate driving, the behavior of this device is similar to that of a MOSFET. Its current-carrying path is very similar to the collector-emitter path of a BJT.

To achieve fast turn-on and turn-off of a BJT, it is necessary to hard drive the gate current in both directions to move the charge carriers into and out of the base region. When the gate of a MOSFET is driven to a high level, a low-impedance path exists from the base of the bipolar transistor to its emitter. This enables rapid conduction of the transistor. Therefore, the higher the gate voltage is driven, the faster the collector current will begin to flow.

When the gate voltage of a MOSFET is pulled low, there will be no current path for the base current in a BJT. The absence of base current triggers the turn-off process; however, to achieve fast turn-off, it is necessary to force current into the base terminal. Since there is no available mechanism to sweep charge carriers from the base, the turn-off of a BJT is relatively slow. This results in a phenomenon known as tail current, as the stored charge in the base region needs to be swept away by the emitter current.

It is evident that a faster gate driving dv/dt rate (stemming from higher gate current capability) will enable faster turn-on and turn-off of an IGBT. However, there are inherent limitations to the switching speed of the device, particularly in terms of turn-off speed. It is due to these limitations that switching frequencies typically range from 20 kHz to 50 kHz, although they can be used for faster and slower circuits in special cases.

IGBTs are commonly used in high-power circuits (Po > 1 kW) in resonant and hard-switching topologies. Resonant topologies minimize switching losses as they are either zero-voltage switches or zero-current switches. Slower dv/dt rates can improve EMI performance (when it comes to such concerns) and reduce the formation of spikes during the conduction and turn-off transitions. This comes at the cost of lower efficiency, as the conduction and turn-off times are longer.

There is a phenomenon known as secondary conduction in MOSFETs. This occurs because the dv/dt rate of the drain voltage is very fast, ranging from 1000 to 10000 V/µs. Although the switching speed of an IGBT is typically not as fast as that of a MOSFET, they can still encounter very high dv/dt levels due to the high voltages involved. If the gate resistance is too high, it can lead to secondary conduction.

In this scenario, when the driver pulls the gate voltage low, the device starts to turn off. However, due to the voltage divider effect of Cgc and Cge, the voltage on the collector rises and generates a voltage on the gate. If the gate resistance is too high, the gate voltage can rise sufficiently to retrigger conduction of the device. This results in high-power pulses, which can lead to overheating and, in certain cases, even damage the device.

Where:

  • dv/dt is the rate of voltage waveform rise on the collector during turn-off.
  • The image represents the gate voltage waveform.
  • Rg is the total gate resistance.
  • Cgc is the gate-collector capacitance. Note that Ciss in the datasheet is the equivalent value of Cge and Cgc capacitances in parallel.
  • Similarly, Rg is the series combination of gate driver impedance, physical gate resistance, and internal gate resistance. The internal gate resistance can sometimes be calculated from the datasheet. If it cannot be calculated, it can be measured by using an LCR bridge with the collector-emitter pins shorted and measuring the equivalent series RC at a frequency close to the switching frequency.
  • If a FET output stage is used, the driver impedance can be found in its datasheet. If it is not available in the datasheet, an approximate calculation can be made by taking the peak driving current at its rated VCC level.

Gate ringing can be eliminated by removing the external gate resistor, which may provide optimal high-frequency performance while ensuring no occurrence of secondary conduction. In some cases, this approach may work, but it can also result in oscillation due to the impedance in the gate driver circuit. The gate driver circuit forms a series RLC resonant circuit. The capacitance mainly originates from the parasitic capacitance of the IGBT. The two inductances shown come from the combination of the board trace inductance and wire bond inductance of the IGBT and the driver.

In the absence of a gate resistor or with a very small gate resistor, the resonant circuit will oscillate and cause high losses in the IGBT. In such cases, there needs to be a sufficiently large gate resistor to suppress the resonant circuit and eliminate oscillation. Since inductance is difficult to measure, it becomes challenging to calculate the appropriate resistor. The best approach to minimize the required minimum gate resistor is to adopt good layout practices. The path between the driver and the IGBT gate should be as short as possible. This applies to the entire path of the gate driving circuit as well as the ground return path. If the controller does not include integrated drivers, placing the IGBT driver near the gate of the IGBT is more important than placing the gate driver’s input near the PWM output of the controller. The current from the controller to the driver is very small, so the impact of any stray capacitance is much smaller compared to the high current and high di/dt levels from the driver to the IGBT. Short and wide traces are the optimal way to minimize inductance.

The typical range for the minimum driver resistor is 2Ω to 5Ω. This includes the driver impedance, external resistor value, and internal IGBT gate resistor value. Once the layout of the board is finalized, the gate resistor value can be determined and optimized.

In summary, this article provides guidelines for the maximum and minimum gate resistor values. Within this range, there is a tuning range that allows fine-tuning of the circuit to achieve maximum efficiency, minimum EMI, or other important parameters. Choosing a safe value between these extreme values in circuit design ensures robustness in the design.