In-depth analysis of the challenges of ESD robust design in analog technology

“With the popularization of portable Electronic products, “smart devices” and automotive electronics, the demand for embedded analog functions in ICs is also increasing. This has driven the demand for specific analog technologies, which account for an increasing proportion of the overall semiconductor market.

“

Author: Gianluca Boselli

With the popularization of portable Electronic products, “smart devices” and automotive electronics, the demand for embedded analog functions in ICs is also increasing. This has driven the demand for specific analog technologies, which account for an increasing proportion of the overall semiconductor market.

With some simplifications, simulation techniques can be divided into three main categories:

High-power BiCMOS: The main target is the RDSON and breakdown voltage of power devices. Usually has a very wide range of component types (bipolar, CMOS, LDMOS and DEMOS devices), covering applications from low voltage (LV, a few volts) to very high voltage (HV, hundreds of volts).

High-speed BiCMOS: The main goal is the speed of bipolar devices to support high-speed applications up to hundreds of GHz.

Analog-CMOS: The main feature is high-density CMOS logic, and low-parasitic, low-noise and high-quality passive components. They are often “derivatives” of CMOS technology.

Electrostatic discharge (ESD) is a transfer of static charge from the body to an object, which generates a high current (a few amperes) in a short period of time (hundreds of nanoseconds). ESD events may be caused by manual handling/testing of the IC during the manufacturing process and may cause catastrophic damage. In order to ensure the robustness of ESD to processing/testing, each IC undergoes standard ESD tests, usually the human body model (HBM) and the charged device model (CDM).

In order to achieve the required level of ESD robustness, a dedicated on-chip Circuit (commonly called “ESD protection” or “ESD clamp”) is added to each pad to absorb ESD energy to a safe level for the protected circuit . In a typical ESD protection implementation, each pad-to-pad combination must have an effective ESD discharge path through ESD protection (Figure 1). Simulation technology poses many challenges to ESD robust design.

ESD technical challenges

A fundamental difference between CMOS and analog technology is that the latter is usually built modularly. This allows IC designers to select only a portion of the available process masks to precisely customize design requirements (not all components available in a given process can be used for design).

From an ESD design perspective, this means that ESD designers must support the same ESD application with different mask sets. This can be very challenging because the actual behavior of ESD protection depends largely on the mask set. In other words, it may be necessary to build multiple versions of the same ESD protection, depending on the mask set available.

Another challenging aspect of simulation technology is the use of models. Although the most advanced CMOS technology has a lifespan of only a few years, analog technology may be used for 10-15 years, or even 20 years. The combination of applications generated during this life cycle is a considerable challenge for ESD design.

ESD design challenges

Drain extension MOS

Drain extension MOS (DEMOS) is a device in which the same type of low-doped region is added to the highly-doped drain region or drain extension region (Figure 2). This will affect the rated voltage (that is, increased breakdown) and drain-gate voltage drop (related to the reliability of the gate oxide). On the other hand, this type of design will reduce the drive current characteristics, because the channel is usually not optimized for this junction. A more complex version, laterally diffused MOS (LDMOS), has better current drive characteristics.

From the perspective of ESD, DEMOS transistors have very low ESD robustness, that is, the ability to withstand high current densities under ESD conditions. The ESD weakness of DEMOS is the main challenge for efficient ESD design, because it requires special ESD protection Circuits, and DEMOS transistors are not used during ESD events (which have an effect on area). In the past 15 years, multiple studies have solved this particular problem, thanks to the use of these components in the most advanced CMOS technology.

A recent job [1] It shows that blocking the silicidation process on the highly doped/low doped drain region (the “SBLK” region in Figure 3) can significantly improve the ESD robustness of DEMOS transistors.

This structure basically increases the resistance on the drain side. Although its specific effects are quite complex, it can be seen as a way to prevent non-uniform current conduction through the ESD current distribution across the width of the device.

The 3-dimensional TCAD electrothermal simulation clearly depicts the uniform ESD current distribution along the entire width of the device and prevents silicidation of the drain region (Figure 4). This will allow some ESD energy to be dissipated by the DEMOS with this structure, thereby reducing the restrictions on ESD protection design.

High voltage active FET

“Active FET” is a very popular ESD protection device, usually used for low voltage applications. The name refers to the fact that the ESD current is shunted through the MOS device in the active mode of operation. This mode is only enabled by the ESD event detector under ESD conditions. The circuit is timed to remain on for the entire duration of the ESD event (1-2 microseconds).

In CMOS technology, the oxide and drain junctions share the same rated voltage, and the on-state is achieved by transiently coupling the drain to the gate. The basic realization of this concept is shown in Figure 5.

For HV devices (such as the aforementioned DEMOS and LDMOS), the drain rating may be much higher than the gate rating (for example, the drain rating is 20V and the gate is only 3.3V). Therefore, the circuit shown in the figure will not work because the drain and gate basically have the same voltage, which leads to gate reliability issues (Figure 5).

A method is needed to divide the pad voltage to achieve an appropriate gate voltage. This can be achieved through the source tracking stage (Figure 6). This solution allows typical high-voltage devices to operate within normal drain and gate operating ratings. In addition, it also provides two significant advantages over the circuit (Figure 5):

The capacitance is much smaller because it drives a much smaller transistor.

The opening/closing time constants are separated and can be optimized separately.

High voltage silicon controlled rectifier (SCR)

The silicon controlled rectifier (SCR) is a pnpn structure. Due to the mutual coupling of the vertical pnp transistor and the lateral npn transistor embedded in this pnpn structure, SCR is the most effective device in terms of ESD power consumption. Once one of the two bipolars opens, it opens the other, and so on.

Referring to Figure 2, it is very simple to integrate SCR into any DeMOS (or LDMOS) by adding a highly doped P-type diffusion in the drain well extension. It can be seen from Figure 6 that a pnpn structure with npn and pnp coupled to each other is formed. In addition, the presence of the gate can be used to further adjust the HV-SCR ESD characteristics.

The basic problem with SCR types is that they can maintain power scaling characteristics [2], Because the pulse width of the applied ESD stress increases.More specifically, based on the maximum power consumed by the SCR under a 100ns ESD pulse, one can expect [2] A certain amount of power is consumed under 200ns and 500ns ESD pulses.

However, the actual maximum power consumption under 200ns and 500ns ESD pulses is much lower than expected (Figure 8). This is a major issue, especially in the case of ESD pulses originating from system-level events, where the stress duration can greatly exceed the duration of a standard HBM event.

High voltage bipolar

As emphasized by HV SCR, high-voltage bipolar devices cannot avoid poor scaling power scaling characteristics. This can be seen in Figure 9, where the actual maximum power consumption does not follow the power scaling law from 100ns.

In addition to the power scaling issues related to HV bipolar devices designed as ESD protection circuits, there is another issue related to HV bipolar that needs to be considered: the parasitic bipolar formed by the N diffusion connected to the adjacent pad .

Referring to Figure 10, the pads (PAD1 and PAD2) usually have ESD protection with reference to the common ground (GND). In the case of an ESD event from PAD1 to PAD2, the ESD current (the solid red line in Figure 10) will flow from ESD protection 1 through common GND and ESD protection 2 to PAD2. Since N diffusion is related to PAD1 and PAD2, a parasitic npn bipolar is now formed (the common p substrate acts as the base of the bipolar), which can conduct current during an ESD event and eventually fail.

The main problem with this configuration is that since ESD current flows in ESD protection 2, the base of the parasitic bipolar (common ground) has a raised potential. This makes the parasitic bipolar very easy to be triggered and therefore easy to fail.

Unlike CMOS technology, in analog technology, it is common to have multiple N-type diffusions to support many different voltage ratings and isolation technologies. Therefore, any N-type diffusion arrangement will produce parasitic effects in a situation similar to that shown in Figure 10. Considering the number of emitters, collectors, base types, and geometric effects, it is very possible to produce hundreds of parasitic bipolars in a circuit for a given technology. This is quite challenging for ESD design, because the ESD protection network must be able to adequately protect the above-mentioned parasitic effects.

ESD qualification challenges “on-chip” system-level requirements

In order to ensure the robustness of the IC manufacturing process to ESD events, HBM and CDM tests were carried out. In the past few years, a new trend that requires system-level ESD protection at the IC level is emerging. Usually system-level ESD protection is solved at the system level by placing a dedicated transient voltage suppressor (TVS) circuit on the circuit board (near the ESD stressor). The rationale behind this trend is that if a single IC has ESD system-level robustness, TVS can be eliminated (thus reducing cost and system design complexity).

Without in-depth discussion of why this reason is flawed, the impact of these requirements on IC-level ESD design is huge, not only in terms of ESD area, but also in terms of design complexity and required learning cycles.

Custom ESD level requirements

Typical ESD-level requirements for IC-level ESD robustness are 2000V HBM and 500V CDM. Although it has been clearly proven that 1000V HBM and 250V CDM provide a very reliable ESD design in today’s manufacturing environment, some customers may require >8KV HBM performance on selected pins to handle unspecified system-level events. The impact of these requirements is also very important in terms of area and development time.

Sustainable Development Strategy

The breadth of the analog technology component product portfolio and the subsequent large number of applications that need to be protected are not suitable for a “single ESD strategy” that meets all requirements. Therefore, ESD engineers in the field of analog technology are studying all ESD protection strategies, carefully weighing the pros and cons to find the most suitable solution.

Active FETs: They are very effective and very popular in low voltage applications. However, for high voltage applications, the combination of low FET drive current and large area makes them less attractive.

Devices based on breakdown: They rely on parasitic bipolar npn or pnp. Due to the excellent area/ESD performance trade-off, Npn-based technology is very popular. The main disadvantage is that it is difficult to control performance through process changes.

SCRs: These solutions are the most effective in terms of area/ESD performance, and they are easy to design. However, from the perspective of DRC-LVS, the inherent risk of latching and the difficulty of achieving it limits their use to some extent.

Self-protection: This solution is very effective in the case of large output drivers, and it can also be designed to withstand ESD events. The disadvantage is that it requires a collaborative design between IP and ESD.

In recent years, the relevance of analog technology has increased rapidly. In this work, we reviewed the ESD challenges related to technology, design, and qualification requirements.