Low power consumption becomes the first choice, so what is IC power consumption control technology?

“Low power consumption is one of the goals pursued by designers. For power consumption, many low-power consumption solutions have been introduced. In order to improve everyone’s understanding of power consumption, this article will introduce IC power consumption control technology.

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Low power consumption is one of the goals pursued by designers. For power consumption, many low-power consumption solutions have been introduced. In order to improve everyone’s understanding of power consumption, this article will introduce IC power consumption control technology.

In many designs, power consumption has become a critical parameter. In high-performance designs, excessive power dissipation beyond critical temperature can impair reliability. This manifests as a voltage drop on the chip, and power consumption can even affect timing because the on-chip logic no longer operates at ideal voltages. To deal with power consumption, designers must build power-sensitive methodologies throughout the chip design flow to handle power.

You shouldn’t wait until it’s almost out to start worrying about power consumption. If so, you may find that too little, too late, is being done to reduce power consumption.

Ignore any factor that consumes power. For example, when you are trying to reduce switching power dissipation, leakage power may be the more important part. Excessive peak power dissipation can cause large noise glitches both on-chip and off-chip.

It is believed that reducing the supply voltage or using a process with a small geometry will solve the power consumption problem. Lower supply voltages reduce noise margins and slow Circuit operation, making it difficult to achieve timing closure or even meet functional specifications. At 90nm and below, there will be greater leakage current.

Count on a “push-button” low-power solution or approach. Power management must be implemented at all stages of the design process – sometimes a design decision, sometimes more automated implementation.

Power-sensitive design and automatic power reduction are considered mutually exclusive. When combined in a complete power management design approach, these two techniques will effectively help you overcome power challenges.

Interconnects are starting to dominate switching power consumption, just as they dominated timing in the first few process nodes. The graph to the right shows the relative impact of the interconnect on the total dynamic power consumption. Today, designers have the ability to reduce power consumption through routing optimization.

In the physical design stage, designers can also find more opportunities for automatic consumption reduction. Automatic power reduction during the physical design process will complement the reduction in power consumption early in the design flow and during logic synthesis.

Power consumption is an “equal opportunity” issue: from early design trade-offs to automatic physical power optimization, all power reduction techniques complement each other and need to be considered as part of every modern design flow. Engineers can apply the following principles as an integral part of any design methodology when addressing power consumption issues.

It should be understood that power consumption is a design parameter as important as performance (timing), functionality, and the cost of your design. Take power consumption into account when making design decisions and trade-offs. Informed design decisions early in the process can lead to substantial power savings. However, automatically reducing power consumption during the initial stages of the design process is more difficult.

Use advanced design techniques to reduce power consumption, such as voltage/power island partitioning, block-level clock gating, power-down modes, efficient memory configuration, and parallelism. High-level abstractions that reduce power consumption include dynamic voltage and frequency scaling, memory subsystem partitioning, voltage/power island partitioning, and software-driven sleep modes.

Accurately estimate power consumption at the RTL and near-RTL levels. It is the designer’s job to understand the design factors and specifications that affect overall power consumption, but it is helpful for designers to have advanced power estimation tools that provide designers with the information they need to make appropriate tradeoffs.

Explore all opportunities to automatically reduce power consumption without compromising timing or increasing area. For example, register clock gating can be used effectively during the logic synthesis stage, but doing so can cause timing and signal integrity issues in the physical design process. An alternative approach is to implement clock gating at the physical design stage, where accurate timing and signal integrity information is already available.

Save power by optimizing interconnects during the physical design phase to reduce capacitance at high-power nodes. Once the interconnect capacitance is reduced, the logic gates driving these lower capacitive loads can be smaller in size or optimized to produce lower power consumption. The use of multi-threshold voltage cell replacement to reduce leakage power consumption can also be effectively implemented at the physical level.