NXP’s Cortex-M MCU based on the SPIFI peripheral completely solves the problem of embedded flash memory selection

The SPI flash interface technology (SPIFI, patent applied for) first adopted by the new NXP ARM Cortex-M3 microcontroller can help 32-bit embedded system designers replace large-size, high-cost serial flash memory with small-size, low-cost serial flash memory. Parallel flash memory. Using SPIFI (pronounced with spiffy, meaning “excellent, neat, beautiful”, etc.-Annotation), the external serial flash memory can be mapped to the microcontroller memory to achieve the on-chip memory read effect. The new technology can solve the problem of external flash memory selection in traditional embedded systems, and provides a new way for designers to reduce size and reduce costs while maintaining system performance.

 

At present, NXP has developed a new peripheral interface technology, which has been successfully applied on the latest LPC1800 microcontroller based on the ARM Cortex-M3 core. Embedded system designers can use this technology to replace parallel flash memory with serial flash memory, reduce package size and reduce system costs. This technology, called SPI Flash Interface (SPIFI), has been patented. Through this technology, the external serial flash memory can be mapped to the microcontroller memory to achieve the on-chip memory read effect. SPIFI provides designers with an innovative solution to simplify configuration, reduce package size, reduce board space and save system costs while maintaining system performance.

 

 

Embedded applications that use 32-bit microcontrollers (MCUs) are currently becoming more and more complex, requiring management tasks for multimedia, photos, and other data-intensive content. Especially for the man-machine interface system, users now hope to have a graphic Display, and realize man-machine dialogue through windows, pictures, animation, sound and other multimedia methods. In addition, with the internationalization of the market, products need to meet the requirements of multiple languages ​​and support various letters and characters. All these put forward higher requirements on system storage resources.

 

Most 32-bit microcontrollers are equipped with on-chip flash memory to support various data-intensive functions, but this kind of memory has limited capacity and usually cannot meet overall application requirements. The on-chip flash memory is usually less than 1Mb. Although it can solve the main application code storage, it cannot meet the storage requirements of other application materials, such as search forms, images, photos, sound files, and multiple languages. For this reason, designers usually use external flash memory.

 

Compared with on-chip flash memory, the cost of external flash memory is much lower, and there are usually stocks of more than 8Mb. The use of external flash memory can increase the flexibility of the system, and the software can be updated while the system is running.

 

 

For external flash memory selection (serial and parallel), designers usually have to comprehensively evaluate and compromise. Parallel flash memory is generally faster than serial flash memory, but requires more pins, PCB layout, and board space.

 

Figure 1 shows the typical data transfer rates of serial and parallel flash memory. For parallel flash memory, the figure assumes that there is no buffering, and the fixed access time is 90ns. Based on the above conditions, the maximum transfer rate of 16-bit parallel flash memory is 22Mb/s. For serial flash memory, the maximum clock frequency of 80MHz per bit transfer rate is 80Mb/s, and the four-channel serial flash memory has a maximum transfer rate of 40Mb/s. Although the control bit is ignored in this calculation, the four-channel SPI flash memory supports the burst bit, and the SPIFI interface supports this function, so the SPIFI interface can reach the above-mentioned transmission rate.

 

As shown in Figure 1, a typical 16-bit parallel flash memory has a transfer rate of 20Mb per second. For systems that use a 32-bit microcontroller and a 32-bit external flash memory communication bus (such as NXP products), designers can choose to use two 16-bit parallel flash memories to achieve a transfer rate of 40Mb/s. However, increasing the speed will also increase the cost. This configuration uses two independent parallel flash memories, and each flash has dozens of package pins. Regardless of the package size, number of pins, or PCB space occupation, it will far exceed the designer’s tolerance.

 

Serial flash memory usually uses a simple four-pin serial peripheral interface (SPI). Considering factors such as space occupation, power consumption, and cost, it is an ideal substitute for parallel flash memory, but the transfer rate is very low. Through Figure 1, we can see that the transfer rate of a typical SPI flash memory at 50MHz is only 5Mb/s, while the transfer rate of a system configured with two 16-bit parallel flash memories is 8 times that. Another problem is that most microcontroller SPI interfaces are connected to the MCU peripheral matrix. Before the processor can access the data, the content must be received by the driver code and stored in the onboard RAM. Since each read of the serial flash memory must pass through the SPI software layer, the speed cannot be improved. For external flash memory applications using a standard SPI interface, the speed may not meet the requirements.

 

The new four-channel SPI flash memory uses an improved 6-pin SPI configuration, and the data transfer rate is much higher than the traditional SPI interface. As shown in Figure 1, the four-channel SPI has a maximum transfer rate of 40Mb per second, which is equivalent to the speed of two 16-bit parallel flash memories. Due to the reduced number of pins and package size, compared with the parallel solution, the four-channel SPI serial flash memory can effectively reduce the cost. Although the four-channel SPI flash memory can completely replace the parallel flash memory in the embedded system, the current 32-bit microcontroller design does not support the maximum transfer rate of the four-channel SPI flash memory. This is mainly because the four-channel SPI interface is connected in the same way as the traditional SPI interface, directly connected to the microcontroller peripheral matrix.

 

NXP’s newly developed SPI flash memory interface (SPIFI) can completely solve the problem of parallel/serial flash memory selection. The patented SPIFI peripheral can map low-cost SPI and the new four-channel SPI flash memory to the ARM Cortex-M3 memory. Compared with the external parallel flash memory solution, the performance loss of MCU using SPI external flash memory is very small. Since the complete memory space of the external SPI flash memory can be mapped to the MCU memory, the microcontroller directly accesses the external flash memory without using software APIs or libraries.

 

For example, using four-channel SPI flash memory, the SPIFI peripheral transfer rate can reach 40Mb/s. Designers can choose cheaper SPI flash memory devices to reduce pin size and simplify configuration on the basis of guaranteed performance. Because the system does not need to use a huge interface design for external parallel flash memory, designers can also choose a smaller and lower cost microcontroller. The use of SPIFI peripherals in embedded systems can improve memory resource utilization, reduce size, improve efficiency, and reduce total system costs.

 

SPIFI peripheral is a dedicated technology first adopted by NXP’s LPC1800 series of ARM Cortex-M3 microcontrollers. In addition, new products on the market also include low-cost Cortex-M0 series and Cortex M4 digital string controller (DSC).

 

SPIFI supports most serial flash memory devices on the market (including four-channel read/write products), configuration programming is very simple, adopts 4/6 pin design (depending on the type of serial flash memory), supports small register sets, and optimizes memory transactions , Its software instructions can reduce CPU overhead and improve memory data exchange efficiency.

 

 

Figure 2 shows the functional block diagram of the SPIFI peripheral. The SPIFI function block is connected to the high-speed bus (AHB) matrix of the microcontroller application, which is mainly used for the processor core and on-chip memory. SPIFI maps the contents of the external SPI flash memory to the microcontroller memory. When the on-chip ROM startup code activates the SPIFI interface, the external SPI memory is completely similar to the on-chip memory on the core processing unit.

 

 

All drivers of SPFI interface are all stored in ROM. For read operations, only one routine call instruction is needed to start the SPIFI peripheral. After the initialization sequence is over, the entire SPI flash memory can be accessed by the processor and/or DMA channel in bytes, half words, and whole words just like normal memory. Erasing and programming can be accessed through simple API commands to access ROM commands. Therefore, there is almost no difference between using external SPI flash memory and on-chip memory.

 

 

For systems that require the microcontroller to boot from an external serial flash memory, the NXP LPC1800 microcontroller has been configured with the SPIFI boot function. There are two methods for selecting the startup source: the first is to use the microcontroller pin to determine the interface of the startup source; the second is to program the startup interface in the non-volatile memory by the user. Programming with non-volatile memory preserves the dual functions of the pins.

 

 

Figure 3 shows the physical interface of the SPIFI peripheral. This example uses a standard 4-pin configuration for traditional SPI flash memory. If it is a four-channel SPI flash memory, two additional pins are needed to support the four-channel function.

 

Different serial flash memory manufacturers and products require different commands and command formats. SPIFI peripherals provide sufficient support for this and are compatible with most SPI flash memory and derivative products to ensure the compatibility of future products.

 

 

The SPIFI peripheral small register group not only guarantees the function of the interface but also simplifies the operation. It controls the SPIFI function through 8 registers, connects to the external SPI flash memory, saves and retrieves data, and monitors operations. Since settings, programming, erasing, etc. are all handled by the integrated ROM API, external SPI memory operations only require a few simple call commands. Overall, SPIFI peripheral configuration is simple and easy to use.

 

 

When the software reads the memory-mapped serial flash memory content, the external flash memory can recognize and accept commands sent by the microcontroller software and automatically sent by the SPIFI peripheral. These commands can be divided into fields such as operation code, address, intermediate and data. The address, middle and data fields are optional fields, which mainly depend on the operation code. Part of the flash memory supports the “read” command to explain the operation code mode to improve system performance. According to different operation codes, data fields can be further divided into input and output data fields. All commands sent to the external SPI flash memory can be processed by calling ROM API commands. The SPIFI ROM API driver allows access to the external SPI flash memory content through a simple load command, ensuring that the application operation code continues to be compact and easy to write.

 

SPIFI software can read external flash memory data and write it to RAM or peripherals without CPU support. For example, for a microcontroller with an integrated LCD controller, this function can improve system performance and save power consumption. The external flash memory can save the image and read it through the LCD controller. Since most LCD controllers read data in order of addresses, SPIFI peripherals can obtain addresses in advance as needed without waiting. The entire operation does not require CPU involvement, nor does it need to load the image into the on-chip RAM, but is directly obtained by the LCD controller. Therefore, the system does not have high requirements for the capacity of the on-chip RAM of the microcontroller, or the existing RAM can be released for other tasks. Since the LCD controller directly obtains the image, the image refresh rate of the LCD display screen is faster, and the simple operation of opening and closing windows appears smoother. In addition, in order to reduce power consumption, the system can also run at a low clock rate, which will not have much impact on display performance.

 

 

From a software perspective, the microcontroller can directly execute the code in the external SPI flash memory. Direct code execution is conducive to online upgrades or to update the factory functions of the on-chip flash memory. The external flash memory can store the verified upgrade code. For example, if the system function address is stored in a table in the on-chip flash memory, the table can be reprogrammed through the routine address of the external flash memory. Or, if the memory page containing the initial information of the original routine is stored in the on-chip flash memory, the memory page can be updated by the new routine that jumps to the external flash memory through the external branch. For the above two cases, because the SPIFI peripheral can implement the direct execution of external flash code, the new code does not need to be loaded into the on-chip RAM.

 

The speed of code execution through external flash memory is far less than on-chip memory. SPIFI peripherals are not designed for real-time running functions that require peak performance, but SPIFI is very attractive for executing non-critical code sequences.

 

 

SPIFI supports writing and executing functions at the same time. In other words, even if the processor is executing on-chip flash code, the external flash memory can be programmed and erased quickly and easily. Because the SPIFI peripheral can run independently and is not affected by the CPU, the system can continue to perform related tasks while programming the external serial flash memory.

 

Since the system can write to the external flash memory while executing key application codes, this function can be used for online software updates. For example, smart meters require uninterrupted work even when updating software. Using SPIFI, the utility company can configure the system, write any code to the external flash memory, without interrupting the metering work of the smart meter, and finally integrate the new code into the system. Similarly, for systems that use a USB port, the new code can be saved in a portable USB drive and then transferred to an external flash memory without interrupting important operations.

 

 

The SPI flash interface technology adopted by NXP LPC1800 ARM Cortex-M3 microcontroller for the first time can map the external flash memory to the microcontroller memory to realize the on-chip memory function. This technology brings designers more options for external flash memory, while reducing system cost and packaging size.

 

The SPIFI peripheral provides designers with a new solution that can use low-cost serial flash memory to replace expensive parallel flash memory, while reducing the size while still ensuring system performance. Many advantages of serial flash memory, such as low cost, small size and simplified configuration, have since been applied, and the impact on system performance is very small. Using SPIFI, designers can also choose a microcontroller without a parallel interface to achieve the required performance in a small, low-cost design.

 

NXP plans to extend SPIFI technology to other Cortex-M products, including low-end Cortex-M0 and the upcoming Cortex-M4 digital signal controller (DSC).