Physical Design of Microprocessor Chip Based on TSMC 180nm Technology

“At present, in the early fire monitoring and alarming of buildings, the wired network is still used. The lines are all over the building, and the initial installation cost is high. At the same time, the line itself is also a great fire hazard. Therefore, a new type of wireless fire monitoring system emerges as the times require. The system is easy and fast to install, and its cost is lower, and it has a larger application space. Microcontroller is one of the core components of the fire monitoring system. General-purpose microprocessors and microcontrollers cannot meet the low power consumption and low cost requirements of the node main control chip in the wireless fire monitoring system.

“

At present, in the early fire monitoring and alarming of buildings, the wired network is still used. The lines are all over the building, and the initial installation cost is high. At the same time, the line itself is also a great fire hazard. Therefore, a new type of wireless fire monitoring system emerges as the times require. The system is easy and fast to install, and its cost is lower, and it has a larger application space. Microcontroller is one of the core components of the fire monitoring system. General-purpose microprocessors and microcontrollers cannot meet the low power consumption and low cost requirements of the node main control chip in the wireless fire monitoring system.

In order to master the core technology of wireless fire monitoring system, establish a software and hardware platform with independent intellectual property rights, and promote the development of wireless fire monitoring system in China, it is necessary to develop a microprocessor for wireless fire monitoring system. This paper completes the physical design of a microcontroller chip dedicated to a fire detection system.

1 SW-A chip architecture

The SW-A chip is a dedicated digital-analog hybrid controller chip based on ARM Cortex-M0 for wireless fire detection systems. Internal frequency division, it can also run at a very low frequency in standby state; a built-in 12-bit successive approximation 8-channel ADC with high sampling rate can sequentially analyze the signals from up to 8 sensors (such as temperature sensor, smoke sensor, light intensity sensor, etc. ) signal is directly sampled, converted and saved, and the detection main program can arbitrarily read the sampled data corresponding to the target sensor for processing and determine whether a fire has occurred.

Built-in 18 KB SRAM, which can be flexibly switched to be used as FLASH and RAM to meet fire monitoring and storage of simple processing programs. It supports ISP (in-system programming) operation and IAP (in-application programming) operation, which not only facilitates the updating and upgrading of the main program of fire monitoring, but also facilitates the optimization of software programming. Interfaces include industry standard UART interface, SSI communication interface (supporting SPI, MicroWire and SSI protocols), and 3 groups (6 channels) PWM. The rich interfaces and function modules make this chip have great potential for function expansion.

2 Physical Design of SW-A Chip

2.1 Physical Design Process Adopted

The physical design of the SW-A chip is carried out with the aid of the EDA tool IC Compiler of Synopsys, using the typical design flow of IC Compiler. Based on TSMC’s 180 nm CMOS process. After the physical design is ready (designing the logic library, setting the physical library, setting the TLU-Plus related files, and setting the gate-level netlist and standard delay constraints read in), the physical design can be started, and the design planning, Placement, Clock tree Syn-thesis, Routing until the design is complete (Chip Finish).

2.2 Design Planning

Design Planning is a very important step in chip physical design; it mainly includes Floorplan and Powerplant.

Usually, before the layout starts, designers often need to spend a lot of time on floorplan and power plan. The quality of the design plan directly determines the power consumption of the chip, the congestion of standard cells, Timing closure, power supply stability, etc. Therefore, design planning is the most repeated and manual design step in the entire physical design process.

The floorplan needs to complete the IO arrangement, PAD placement, Macro (including analog modules, storage units, etc.) positioning, as well as the chip shape, congestion and area settings. As a user-oriented control chip, the layout of IO must comprehensively consider user needs and design requirements, and the vertical and horizontal dimensions of PADs with different functions are also different. In this paper, PADs with larger vertical and horizontal dimensions are placed on the north and south sides of the chip, and PADs with smaller unidirectional dimensions are placed on the east and west sides of the chip with the large side facing north and south (see Figure 2(a)). Compared with The PAD with larger bidirectional size is placed around the chip (see Figure 2(b)). This design reduces the chip area very effectively.

Macros that need to be positioned in this chip include SRAM, ROM, ADC and ANALOG_TOP. This article comprehensively considers their positional relationship with IO and positions them around the chip, so that a blank area in the chip can be reserved to place standard cells. In order to ensure the interconnection between Macro and PAD and standard units, there is only one blank area around each Macro, and standard units are not allowed to be placed in this area under any circumstances. The specific commands are as follows:

In this chip, a 40 μm reserved area is designed between the core area and the PAD where standard cells and Macros are placed, for placing the power ring (PowerRing) and interconnecting lines. In order to prevent the overlapping of standard cells, use the command to ensure that standard cells can only be placed in channels with a height greater than 10 μm. After setting the chip floorplan, you can use the command creat_fp_placement for pre-layout. This chip is designed and produced using TSMC 180 nm process, the working voltage is required to be 1.8 V, and the maximum voltage fluctuation that can be tolerated is ±10%. Therefore, when planning the power supply, this paper comprehensively considers the power supply requirements of the chip and the voltage drop caused by the interconnection line ( IR-Drop) and a smaller power network area, two power rings and 14 power strips (Strap) are designed. After analyzing the power network (Analyze Pow-er Network), the maximum IR-Drop of this design is 29.7 mV. Figure 3(a) is the design plan of the chip, and Figure 3(b) is the voltage drop distribution diagram of the chip.

2.3 Layout

The quality of the placement is the key to the success or failure of the physical design of the chip. The main task of the layout is to complete the placement of the standard cells in the design and to fix the setup time. Before the layout officially starts, you need to use the command check_physical_design to check whether the layout preparation is complete. It must be ensured that: the positions of all Hard Macros and IOs are fixed; all logical pins and physical pins in the design correspond one-to-one; all logical units have corresponding physical units; all units in the design are fixed in size. In order to facilitate interconnection and routing, before starting to place standard cells, a specific area in the chip can be set as a Place-ment Blockage. Various forms of restrictions on ICC tools, such as prohibiting the placement of standard cells during rough layout, allowing only standard cells during layout optimization, and only allowing wiring, etc. In this design, multiple layout restriction areas are set to facilitate ADC, ANALOG_TOP, etc. and IO (see Figure 4(a)).

After the layout is ready, you can use the command place_opt to place it with additional constraints, which performs coarse place, high-fanout net synthesis, physical optimization until legalization, The position of the unit is determined by the first three steps (see Figure 4(b)), and the standard unit is finally correctly placed in the calculated position through legalization (see Figure 4(c)). The specific commands for the physical design of this paper are as follows:

The tool is required to repair other areas except the critical clock path, and the effort is high. The option “-congestion” is used to control the tool to reduce the congestion of the chip as much as possible to facilitate subsequent routing, and the option “-pow-er” is used to control the tool to optimize Leakage power, dynamic power, and low-power placement.

After the layout is completed, the area utilization rate of the chip is shown in Table 1. The congestion degree is concentrated between 0.625 and 0.875, and the congestion degree is moderate. Neither the chip area is wasted because the chip utilization rate is too low, nor the congestion is too large. This leads to subsequent design difficulties or even redesign.

2.4 Clock Tree Synthesis

One of the main tasks of Clock Tree Synthesis is to control the clock skew within an acceptable range to ensure that the chip works efficiently and without errors. The clock tree synthesis strategy of this chip is as follows: the logical synthesis of the clock tree (clock-cts), the physical synthesis of the clock tree (clock-psyn), and the routing of the clock tree (clock-route). The logic synthesis stage of the clock tree only completes two tasks: by calculating the delay on each clock path, the position and size of the buffer (buffer, inverter) need to be inserted (controlled by the -only_cts command option); due to the function of the clock network. Power consumption accounts for a very large proportion of total power consumption, so power consumption optimization (-power) must be performed during clock tree synthesis. No routing is performed at this stage. The specific commands are as follows:

The physical synthesis phase of the clock tree places the inserted buffers in the correct positions, performs RC extraction, and checks the maximum insertion delay, minimum insertion delay, maximum clock skew, and maximum transition time of the clock network with reference to the delay constraint file (SDC). And repair the hold violation in the design. In order to facilitate the non-clock network routing, the -ar-ea_recovery option needs to be added at this time to reduce the wiring area. The power consumption is still optimized at this stage. When completing the clock tree routing, this paper uses the arnoldi model to accurately calculate the clock tree delay and 15 loop iterations for clock routing. Table 2 shows the timing of this design before clock synthesis. It is obvious that there are multiple critical paths and there are many setup time violations; after clock tree synthesis is completed, clock check is performed, and no clock violation is found, indicating that clock tree synthesis is completed.

2.5 Routing and chip completion

In this paper, routing and its optimization are done separately. First, global routing, detailed routing and search & repair are completed in the initial routing stage, and then the topology algorithm is used to optimize the routing. Current leakage power consumption is optimized. In order to prevent the occurrence of the antenna effect, the chip is designed to repair the antenna effect during the chip completion stage. At this time, there are still blank areas in the chip, and the filer needs to be filled to meet the requirements of DRC. Figure 5 is the physical design layout of the chip, and Table 3 is the area and power consumption of the chip. It can be seen that the total area is 2 794 371.012 703 μm2, and the total power consumption is 11.635 4 mW. After simulation, it is proved that the chip operates at a clock frequency of 50 MHz. It works normally and meets the design requirements, which proves that the design is correct and effective.

3 Conclusion

Based on the TSMC 180 nm process, this paper completes the physical design of a microprocessor chip used in a wireless fire monitoring system. After using different strategies to complete the design steps of the chip’s floorplanning, layout, clock tree synthesis and wiring, the results are obtained. The layout, area, power consumption and other reports of the chip, after the physical design, the design indicators of the chip meet the design requirements, which proves the correctness of the physical design of the chip.