Reliability Assessment of SiC MOSFETs Under Repeated UIS Stress

Silicon carbide (SiC) devices, due to their superior performance, are particularly suitable for use in high-power, high-temperature, and high-switching-frequency applications. In recent years, significant progress has been made in the development of SiC devices, especially in terms of their reliability, making SiC-based devices a viable alternative to silicon-based power devices.

However, even with these advancements, SiC devices still face reliability issues in some extreme operating conditions such as overcurrent, overtemperature, short circuits, and non-clamped inductive switching, which hinder their full replacement of silicon-based devices.

For instance, electric motors experience sudden high current and voltage pulses during startup or load variations. Despite well-designed inverters or power supplies, parasitic inductances in the circuit can lead to high voltage spikes. These voltage spikes can easily exceed the maximum breakdown voltage, causing avalanche breakdown in a short period. This stress can lead to parameter drift, limiting the operational range and lifespan of the components.

The device under test is connected to the power supply through inductors and high-speed switches. When the switch is closed to initiate device operation, the current starts to rise linearly. Upon reaching the predetermined experimental current, the device is turned off along with the switch.

The magnetic field in the inductor generates a back electromotive force (EMF), resulting in a very high voltage across the device. Without protective circuits in place, all the energy stored in the inductor gets discharged directly into the device.

Figure 1: UIS Test Circuit

Typical UIS Curve for SiC MOSFET

Measurements of device characteristics before and after each pulse sequence reveal the gradual impact of repeated UIS stress. After undergoing millions of pulse cycles, the comparison of I-V curves for the device before and after stress is shown in Figures 3 and 4.

Figure 3: Drain-Source Voltage I-V Curve

Figure 4: Source-Drain Voltage I-V Curve

Repeated UIS pulses cause a slight drift in threshold voltage and lead to a decrease in on-state resistance, which is evident in the output characteristics. The reduction in on-state resistance indicates that the characteristics are unaffected by thermal cycling.

During the avalanche phase of UIS pulses, a large number of high-energy charge carriers are generated near the blocked PN junction. The drift in threshold voltage suggests that positive charges are trapped at the channel-gate interface or nearby. The origin of these positive charges can be attributed to the formation or activation of electrically active defects in the gate dielectric caused by the formation of high-energy holes during the UIS pulse process.

Changes in drain current characteristics are induced by an increase in electrically active trap density, manifested as an increase in drain current itself and a change in the shape of the I-V curve, likely due to changes in charge distribution and resulting electric field distribution.

Repetitive avalanche stress significantly affects the electrical performance of the tested device. After undergoing repeated UIS stress tests, the device exhibits a consistent degradation trend, characterized by a decrease in threshold voltage, reduction in on-state resistance, and a significant increase in drain-source and gate-source leakage currents. Prolonged repetitive UIS stress also notably increases the turn-on time.

Hence, besides conventional reliability considerations, SiC MOSFETs require specialized testing approaches based on the unique characteristics of SiC to effectively assess their reliability.