The trade-offs and technologies needed to increase power density

“Constrained by limited space, reducing the size of the power supply is often the key to a successful design. There is always a challenge to achieve more power in a smaller space. More broadly, the miniaturization of power devices will continue to drive new markets and applications on top of existing ones.

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Constrained by limited space, reducing the size of the power supply is often the key to a successful design. There is always a challenge to achieve more power in a smaller space. More broadly, the miniaturization of power devices will continue to drive new markets and applications on top of existing ones.

Power densities have become higher and higher, an industry trend that has become an indisputable fact over the decades and is expected to continue. Figure 1 shows how the converter size of a 6A to 10A power module continues to decrease over time. Advances in technology can allow for a reduction in size or a dramatic increase in power output capability. Each solid line represents a new generation of technology and demonstrates Related benefits of increased power density.

Figure 1. With the development of new generation technologies, the size of power Modules will decrease over time.

Increases in power density are often tied to developments in other areas such as efficiency or cost. In general, a fundamental increase in power conversion efficiency can reduce the size of the solution. The reduction in size brings a series of knock-on effects, resulting in cost savings from fewer physical materials, fewer components, better cost structure, more solution integration, and lower total cost of ownership.

What is power density?

Power density is a measure of how much power can be handled in a given space and can be quantified as the amount of power handled per unit volume, measured in watts per cubic meter (W/m3) or watts per cubic inch (W/in3). These values ​​are calculated based on the converter’s power rating and the “box volume” (length x width x height) of the power solution (all components included), as shown in Figure 2. Units can be scaled to the appropriate power class or size. For example, kilowatts per liter is a common figure of merit (FoM) for EV onboard chargers, as these power converters deliver kilowatt-level power (between 3kW and 22kW).

Current density is a useful metric related to power density and can be quantified as current per unit volume in amperes/cubic inch or amperes/cubic millimeter. The converter’s current rating (usually the input current or output current) can be used to calculate the current density. The current density is usually the FoM that is more suitable for applications such as point-of-load regulators. The size of these designs is proportional to the output current, and the output voltage level is typically low, around 1V. Power density values ​​can be artificially inflated by assuming an unrealistically high output voltage. Therefore, current density is a more effective metric because it excludes output voltage from consideration.

Sometimes bulk density doesn’t matter. Power electronics may not be limited in height because other parts of the design will be quite tall. Instead, board area may be the limiting factor. In these cases, increasing power density may require finding ways to stack or 3D integrate components to reduce the space footprint of the power solution. You can then modify the metrics used to compare solutions to watts per square millimeter or amperes per square inch to highlight key design goals (as shown in Figure 3).

Depending on the application, power density can be viewed in several different ways, but the goal is the same: reduce solution size to increase power density. The question now is how to get those benefits from power density.

What factors limit power density?

For years, engineers and researchers have been working to find ways to increase power density. This is a tough task. Most companies focus their research on reducing the size of passive components used for energy conversion. Inductors, capacitors, transformers, and heat sinks typically account for the largest portion of the power solution size, as shown in Figure 4. semiconductor switches and control Circuits are smaller and more integrated.

How to reduce the size of passive components? A simple solution is to increase the switching frequency. Passive components in switching converters store and release energy during each switching cycle. The higher the switching frequency, the less energy it stores per cycle. For example, according to Equation 1, the design formula for an Inductor in a buck converter:

where L is the inductance, D is the duty cycle, ΔIL is the inductor current ripple, FSW is the switching frequency, and VL is the voltage across the inductor. The required inductance (L) is inversely proportional to the switching frequency (FSW). As the switching frequency increases, the inductance decreases. The smaller the inductance, the smaller the inductor required and the more space-saving it is. Figure 5 illustrates the difference in inductor size required to switch a 3A, 36V converter at 400kHz versus 2MHz.

Higher switching frequencies have other size advantages. Increasing the switching frequency increases the control loop bandwidth, allowing the transient performance requirements to be met with a smaller output capacitor. You can design differential-mode electromagnetic interference (EMI) filters with smaller inductance and capacitance, and use smaller transformers that do not saturate the core material. So why can’t one just rely on increasing the switching frequency to increase power density? As it turns out, that’s easier said than done. Even if all the passive components used in power converters are reduced to negligible size, there is still an opportunity to reduce the size of the power solution. Power switches, gate drivers, mode setting resistors, feedback network components, EMI filters, current sensing components, interface circuits, heat sinks and many other components take up valuable space. All of these aspects of overall power supply design are areas where innovation can be used to increase power density. Let’s review the main factors limiting a designer’s ability to increase power density.

Factors limiting power density: switching losses

Although increasing the switching frequency can improve power density, at present, power converters are generally not switching above the megahertz range because: Increased switching frequency has undesirable side effects, as well as increased switching losses and associated temperature rise. This is mainly caused by some major switching losses. To understand these switching losses, it is necessary to first introduce some industry terminology. In a semiconductor device, the amount of charge associated with the device is generally related to the on-state resistance. Lower resistance results in higher gate charge and parasitic capacitance. This trade-off of resistance and charge is usually quantified by RQ FoM, which is defined as the on-resistance of the device multiplied by the total charge, where the total charge is the charge that must be supplied to the terminals to switch the device on and off at the operating voltage. In addition, the area occupied by the device to achieve the target resistance is often referred to as the product of resistance and area (Rsp). You can reduce conduction losses by reducing the on-state resistance (RDS(on)) of a metal-oxide-semiconductor field-effect transistor (MOSFET). However, reducing RDS(on) will also result in increased losses associated with device switching and increase the overall die area and cost. Depending on the implementation and application, the effect of different switching losses on the overall power loss may vary. See the application report “Power Loss Calculations and Common Source Inductance Considerations for Synchronous Buck Converters” for more details on each type of loss. For the purpose of illustrating the point of this article, let’s look at an example of a buck converter and focus on the key limiting factors associated with each loss component.

Key Limiting Factor 2: Reverse Recovery Losses

In a buck converter, reverse recovery occurs when the high-side MOSFET turns on and the body diode of the low-side MOSFET conducts current, forcing a rapid transition of the low-side diode current to the high-side MOSFET. During this transition, current is required to remove the low-side diode minority charge that causes direct switching losses. See Equation 4:

One of the best ways to reduce the effect of diode reverse recovery is to optimize the MOSFET design to reduce the stored charge (QRR), or to reduce or eliminate the rising edge dead time to completely eliminate the effect of losses.

Key Limiting Factor 3: Turn-On and Turn-Off Losses

The parasitic loop inductance causes many switching-related losses, which can greatly reduce efficiency. Let’s take the example of a buck converter again that conducts inductor current through the high-side MOSFET. Turning off the high-side switch interrupts the current flow through the parasitic inductance. Transient currents (di/dt) and parasitic loop inductance can cause voltage spikes. The higher the di/dt value, the lower the switching losses, resulting in higher device voltage stress. At certain turn-off speeds, the buck converter high-side switch can shoot through. Therefore, you must carefully control the switching speed to maximize efficiency while keeping the DC/DC converter within a safe operating area. In addition, reducing the drain charge of the high-side MOSFET will also cause additional voltage spikes to appear on it, since there is less capacitance to absorb the energy stored in the parasitic loop inductance as part of the inductor/capacitor network. This presents another challenge, so it is best to keep the drain charge as low as possible to reduce the aforementioned charge-related losses. Mitigating the overall losses associated with these parasitics often requires reducing the loop inductance itself, along with other gate driver technologies.

Factors Limiting Power Density: Thermal Performance

In the previous section, we focused on the key mechanisms that generate switching-related losses in DC/DC converters. Another key factor that affects the overall power density is the thermal performance of the system. The better the heat dissipation of the package, the more power loss can generally be tolerated without unreasonable temperature rise. These factors are often included in data sheet parameters, such as junction-to-ambient thermal resistance (RΘJA), and careful estimation of application conditions.

The overall goal of thermal optimization of the package and printed Circuit board (PCB) is to reduce power converter losses while reducing temperature rise. With the trend towards miniaturization and cost reduction in power supply designs, the overall size of DC/DC converter solutions has shrunk. This makes system-level thermal design increasingly difficult, as smaller die and package sizes typically result in poorer thermal performance, as shown in Figure 6.

Figure 6 clearly shows that as package size, die size, and overall power density increase, expected thermal performance degrades rapidly unless you prioritize innovative packaging. And as the overall power density increases, the expected thermal performance degrades rapidly unless you prioritize innovative package thermal performance (dissipating heat away) and reducing power loss (generating less heat).

How to Break Through the Barriers Limiting Power Density

Focusing on any of the key factors discussed above can improve the overall power density of the device. However, to truly achieve power densities that were previously unattainable, you must do multiple things in parallel to overcome each factor limiting power density: reduce switching losses; improve package thermal performance; employ innovative topologies and circuits; and finally But an equally important way is integration.

Switching Loss Innovation

Investing in semiconductor technology is clearly necessary to achieve excellent device performance and FoM. This may include innovations to improve existing technologies, or the development of new materials with inherently better performance, such as Gallium Nitride (GaN) technology for higher voltage switching applications. Figure 7 compares a 3.3V to 1.8V buck converter using different power processing technologies from Texas Instruments. The TPS54319 uses TI’s previous power processing node, while the TPS62088 uses TI’s latest power processing node, which has a lower RQ FoM. As shown in the efficiency curve, the TPS62088 is able to switch at 4MHz while maintaining nearly the same efficiency compared to the TPS54319, which switches at 2MHz. This can halve the size of the external inductor. In addition, the overall package size has been reduced from 4mm2 to 0.96mm2 because TI’s new power processing node can also significantly reduce Rsp. While this size reduction is very attractive from a power density standpoint, it also presents challenges related to temperature rise, which we will discuss in the next section.

GaN’s unique combination of zero reverse recovery, low output charge, and high slew rate enables new totem-pole topologies such as bridgeless power factor correction. These topologies have higher efficiencies and power densities not possible with silicon MOSFETs. Figure 8 shows a direct comparison of TI’s GaN technology at 600V with industry-leading silicon carbide (SiC) and superjunction silicon devices.

Packaging Thermal Innovations

The ability to dissipate heat from an integrated circuit (IC) package directly affects power density. As we mentioned earlier, this issue is becoming more and more important as package sizes continue to shrink. Also, in a typical power converter, the semiconductor device is often the hottest part of the solution, especially as Rsp shrinks rapidly. TI has invested in the development and introduction of the HotRod™ package, which replaces the typical bond wire quad flat no-lead (QFN) package with a flip-chip package. Figure 9 shows how the HotRod QFN eliminates the bond wire situation while maintaining a QFN-like package. This greatly reduces the parasitic loop inductance commonly found in flip-chip packages, while retaining some of the thermal performance benefits of QFN packages.

Figure 10 shows TI products that incorporate these technical enhancements. As you can see, the package helps to implement a large DAP at the center of the package. Compared to the previous generation, this DAP has about a 15% temperature rise advantage.

Likewise, when using wafer chip scale packaging (WCSP), most of the heat is conducted directly from the bumps all the way to the PCB. The larger the bump area in the WCSP package, the better the thermal performance. TI recently developed and released the PowerCSP™ package, which is designed to improve the thermal and electrical performance of the package by replacing some of the typical round bumps in WCSPs with large solder bars. Figure 11 illustrates an example implementation of this technique in the TPS62088. Figure 11a shows the standard WCSP package, while Figure 11b shows the same device in a PowerCSP package. As you can see, without any other changes to the system, the temperature rise is reduced by around 5%.

Advanced Circuit Design Innovations

An undesirable consequence of lower Rsp and lower RQ FoM is the effect of turn-on transition losses at reduced drain charge. From Figure 12, you can see that for a fixed amount of voltage overshoot, the turn-off losses of this buck converter increase significantly as the drain charge decreases. When it comes to this trade-off, while the performance of RQ FoM MOSFETs continues to improve, new advanced gate driver intellectual property (IP) is required to switch the MOSFET as quickly as possible, while keeping it in electrically safe operation within the range.

In this regard, TI has recently developed a range of gate driver technologies that, despite lower RQ FoM MOSFETs, can still achieve very fast switching speeds, resulting in better charging and switching losses, while still keeping the MOSFET at its within the scope of electrical safety. As you can see when comparing Figure 13a and Figure 13b, the turn-off energy loss can be reduced by 79% while keeping the peak voltage stress constant. In some designs, as shown in Figure 13b, this loss reduction can yield up to a 4% increase in efficiency at the peak efficiency point.

In addition to advanced gate driver technologies, there are numerous opportunities to increase power density through topological innovations. Figure 14 shows a flying capacitor four-level (FC4L) converter topology that achieves a number of key power density advantages, including increased device FoM by reducing device voltage ratings, reducing magnetic filter size, and improving thermal distribution. These advantages translate into improved power density, as shown in Figure 15. By using this particular topology, the TI solution combines the benefits of GaN with advanced packaging techniques to significantly reduce the size compared to other topologies using SiC.

Integrated innovation

The final way to achieve optimal power density is integration. Cost-effective integration reduces parasitics, reduces bill of materials, increases efficiency and saves space. Integration can be applied to multiple aspects of power management. It may require adding more circuitry to the IC, adding more components to the package, or packing more components into the power solution by other physical or mechanical means. Some examples of technology leadership in this area include drivers integrated with GaN FETs, capacitor integration to reduce critical loop inductance, and 3D stacking of passive components. There are many benefits to adding gate drivers with switching power FETs. The switching gate drive loop inductance is reduced, resulting in higher switching speeds, more stable operation, and fewer components. GaN FETs in particular benefit from this integration. Devices such as the LMG3410 also include additional features such as overcurrent protection, thermal protection, and monitoring (see Figure 16). This integration greatly simplifies power management solutions and enables designers to implement all the features GaN has to offer.

The UCC12050 utilizes the integration of magnetics to provide isolated bias power without the need for an external transformer. This approach reduces size and design complexity and reduces EMI.

A final example achieved through integration is the 3D stacking of components, which typically occurs in power modules with integrated passive components. Figure 18 uses the TPS82671 as an example. The device embeds a power IC in a laminate substrate with an inductor and input and output capacitors placed on top. This minimal solution requires no additional components. Simple integration concepts can achieve amazing results, saving PCB area and simplifying power solutions.

concluding remarks

Obviously, the development trend of the whole industry is getting higher and higher power density. There are some major limitations to enabling more compact power solutions. Overcoming power loss and thermal performance challenges requires innovation in switching performance, IC packaging, circuit design, and integration. Each approach has its own opportunity to significantly improve power density, but each technology in turn merges with each other. Therefore, by combining technologies from each class, power density can be significantly improved. Imagine what we can finally achieve with excellent switching device FoM and industry-leading package thermal performance, using a multi-stage topology and passive integration for lowest loop inductance. Technological advancements interact and ultimately achieve breakthroughs in power density. Leveraging TI’s advanced process, packaging and circuit design techniques, it is now possible to achieve more power in a smaller space and enhance system functionality at a lower system cost.