Winning the Global Semiconductor Technology Competition with Virtual Process Modeling

“The development of semiconductor processes is by no means easy, and the difficulty and cost of each generation of device research and development are constantly increasing. The traditional build-and-test approach to developing state-of-the-art processes is too time-consuming and cost-prohibitive to apply today.

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The development of semiconductor processes is by no means easy, and the difficulty and cost of each generation of device research and development are constantly increasing. The traditional build-and-test approach to developing state-of-the-art processes is too time-consuming and cost-prohibitive to apply today.

High cost of process development

Most chip designers need to develop new products based on existing manufacturing processes, but the processes themselves also require engineers to develop. Process development, compared to designing new chips, requires engineers and their skills to be completely different. The goal of the former is to create new semiconductor manufacturing processes that not only meet device performance requirements but also ensure high yields.

In the past, developers needed to prepare multiple test wafers to determine the best process requirements for a particular device. They need to fabricate a set of wafers, analyze them, and then use the results to improve the next round of manufacturing process steps. As feature sizes shrink, the process for each update becomes more sensitive to variables. Features and parasitics that may have been overlooked in previous development must also be considered when testing, further increasing the complexity and data volume of testing. The time and cost of repeating this process in cycles until the entire process flow is finalized makes it almost impractical to use such an approach at the most advanced technology nodes.

Testing with virtual wafers

Today we can replace this time-consuming and costly traditional method with virtual manufacturing. Virtual manufacturing refers to the computer simulation of the process of manufacturing real wafers (as shown in Figure 1). Semiconductor process engineers can use virtual models to test various configurations of manufacturing equipment with far more variables than real-world testing. By simulating the entire process flow, designers can virtually manufacture thousands of wafers in days, not months. Visualizing the process flow with graphic animations can help them quickly understand the situation, adjust process recipes and device integration plans, and evaluate the impact of each adjustment on electrical performance.

Figure 1. Graphical animation of semiconductor process steps in virtual manufacturing

Leveraging Virtual Wafer Manufacturing Statistics to Improve Yield

Statistical analysis based on large amounts of data can give developers more confidence in the selected process setup. Modeling of virtual manufacturing can incorporate defects and random variations that cannot be simulated under real-world conditions, allowing developers to test the sensitivity of device architectures to various unpredictable factors in the process flow.

There are several ways to optimize a process setup for a new memory or logic manufacturing flow, the simplest of which is to select a variable and study its impact. Take the critical dimension (CD), for example, the dimension of the device feature that guarantees the desired electrical performance. Developers can set a specific size range from low to high and then test the effect of different size values ​​within that range on device performance (such as threshold voltage). They can also use these modeling to test the interaction between cross-processes. effect.

However, the above methods are not sufficient to study the intricate interactions between the individual process steps and the final structure. The second method we will use is Monte Carlo analysis, which randomly varies various process and device parameters and calculates the final device geometry and performance (as shown in Figure 2), which can automatically define the required process and design parameters to meet specific yield and performance requirements. This is arguably the primary use case for virtual technology, ideal for testing the interaction of many different processes.

Figure 2. Statistical experiment based on virtual manufacturing

SEMulator3D® for Virtual Manufacturing

SEMulator3D is a virtual manufacturing platform developed by Coventor, a subsidiary of Lam Group, which can be used to define all process steps as well as device modeling, metric data collection, electrical and device analysis, statistical analysis of results and process visualization based on graphic animations. Today, many semiconductor companies are using the platform to optimize and scale advanced process nodes and develop advanced new technologies like GAA (Gate All Around) transistors (shown in Figure 3).

Figure 3. Fully Surrounded Gate Transistor via SEMulator3D

Such virtual manufacturing technologies represent the future of semiconductor process development, enabling new processes to come to market months earlier and creating a market opportunity of hundreds of millions of dollars for leading semiconductor companies.